SoCs lend momentum to design-for-test solutions

SoCs lend momentum to design-for-test solutions
By Jerry Ascierto, EE Times
June 5, 2001 (2:27 p.m. EST)
URL: http://www.eetimes.com/story/OEG20010605S0048

SAN MATEO, Calif. — As built-in, self-test technology continues to gather steam, BIST providers from a variety of application bases are preparing to show their arsenals at the Design Automation Conference (DAC) in Las Vegas later this month.

While still-emerging, BIST has been seen as an alternative to the rising, sometimes prohibitive cost of "big iron" automated test equipment (ATE). As test costs continue to rise to levels that match those of chip design and manufacturing, the concept of embedding testers on-chip grows more attractive.

LogicVision Inc. (San Jose, Calif.) will ride a wave of partnerships into DAC. Seeking to propagate its software across a spectrum of ATE and chip companies, the embedded test provider has recently signed partnerships with FPGA maker Actel Corp., ATE giant Advantest Corp., and ATE provider SZ Testsysteme AG (Amerang, Germany).

"Our goal is to be hardware-agnostic, to be agnostic in the manufacturing space," said Rodger Sykes, vice president of business development at LogicVision. "We want to enable the whole manufacturing environment. We are continuing to sign up LogicVision partnerships, and have already signed up Teradyne, Credence, LTX, [and] Advantest and we're currently in discussions with Agilent."

In its deal with Actel, LogicVision is looking to develop an embedded self-test solution for users of Actel's Varicore programmable gate array cores. The deal with SZ will marry LogicVision's on-chip test technology with the German company's off-chip, mixed-signal automated test equipment.

In the midst of readying itself for an initial public offering, LogicVision said it will offer DAC attendees a glimpse into its latest development, a new product based on programmable-memory BIST technology.

The complexity of testing system-on-chip devices has been a focus of other companies as well. Fluence Technology, with expertise in the mixed-signal arena, will today roll out ADCBIST intellectual pr operty that lets engineers implement a BIST methodology for at-speed testing of A/D converters in SoC designs.

In conjunction with that release comes the ADCBIST Developer, a software tool that allows designers to determine BIST requirements and to simulate performance of A/D converters before first silicon.

"Our claim to fame with ADCBIST is really twofold," said Mike Kondrat, vice president of marketing for Fluence (Beaverton, Ore.). "If you implement this on a chip, the chip basically tests itself. It outputs analog information in digital format, reducing the need for complex analog instrumentation. It's a histogram-based, analog BIST. Instead of taking tens of thousands of bytes of data, we gather a histogram in performance of the circuit under test."

ADCBIST generates results for the A/Ds embedded in SoC designs that can be transferred directly to test programs for digital ATE, effectively eliminating the need for mixed-signal ATE. The ADCBIST Designer software is priced at $35,000, and is available immediately.

SynTest Technologies Inc. (Sunnyvale, Calif.) also sees opportunity in the rising complexity of SoC designs. The 11-year old company, which is preparing for an initial public offering on the Taiwan stock exchange, has just signed a deal to provide design services and solutions for customers of Bops Inc., a DSP core provider. SynTest said it has been making strides for Verilog and VHDL designs with its TurboBIST-Logic tool.

Already used by LG Electronics for an HDTV chip and by Mindspeed Technologies for a 5 million-gate switch fabric chip, TurboBIST-Logic is intended to enable at-speed testing of multiclock logic circuits, including complete SoCs. Used in conjunction with SynTest's scan ATPG technology, or its boundary-scan and memory-BIST products, SynTest claims to achieve 99 percent plus fault coverage.

"If SoC designers don't have an overall DFT plan, it could be a disaster," said L.T. Wang, president and chief executive officer of SynTest. "From an IP core point of view, because the core was not developed by the designer, because it was purchased from somewhere else, in order to test the core, it must be isolated. And right now, some designs have an internal clock rate of 1 GHz, but a similar device could be at 400 MHz, or 200 MHz. So the test cost will be a problem if you try to use a 1-GHz tester to test every chip.

"Testing at operational speed is essential for complex chips, where path delays and timing faults are crucial," Wang said. "Only a full-clock speed or at-speed testing will find these. TurboBIST can test a circuit at its full-operational speed, which isn't possible using scan-based ATPG alone."

SynTest has been working with Bops to provide its scan and memory BIST services to some Bops customers, and will now offer them design and support services as well.