English
Reduce embedded SoC design cost & optimize IP integration
Neil Hand, Cadence Design Systems
EETimes (8/9/2010 6:45 PM EDT)
Over the last decade a fundamental shift has occurred in system-on-chip (SoC) design. This shift has largely gone unnoticed and has introduced significant unnecessary costs and inefficiencies into the design process – costs that must be eliminated if SoC design is to remain viable for a wide range of companies.
In the past, most of the design effort in an SoC was centered on creating unique new logic that differentiated the design from other designs available. It has been this understanding of SoC design that drove the evolution of design tools and technologies over the past decade – the focus on new logic creation. Fast-forward to today and we find a very different situation, with SoCs that contain large amounts of internal and third-party intellectual property (IP) integrated into complex systems. With this change, much of the design effort is now spent on integration, verification, and software development, with little in the way of tools and technologies to automate this integration.
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