SANTA CLARA, Calif. Industry improvements in the quality of intellectual property and tools were the topics of discussion at the International Symposium on Quality Electronic Design. Speakers at an afternoon plenary session called for improvements in chip yield, tool development, tool flows and methodologies, as well as for the use of an embedded test strategy.
Philippe Magarshack, group vice president of R&D design automation and libraries at STMicroelectronics, spoke of his company's experience with bad intellectual property.
"Our experience with IP has been extremely negative so far," said Magarshack. "We need IP quality metrics badly we need someone like [the Virtual Socket Interface Alliance] to help out."
Magarshack said the company has had bad experiences with using both internally developed as well as third-party IP.
"We purchased a core from one vendor and the core won't compile," said Magarshack. "But we really n eed the block for this particular project, so we are working with the vendor to fix the thing. Internally it is even more difficult because the original core developer's life doesn't depend on it like a third party."
Magarshack also said his company is constantly struggling with the infamous design gap how design automation lags gates available.
"SoC design quality to me means creating a reproducible process to get the right design at the right time," he said. He noted that the EDA industry is starting to address the real problems, but just not fast enough.
"We've found that the timing convergence is a solved issue, at least at 0.18 micron, and crosstalk-correct design is being handled adequately," said Magarshack. "But now we have new tool problems."
Magarshack said ST needs design database tools that can handle 100-plus Gbytes and public design database application programming interfaces. "And IR drop analysis must become as mandatory as [layout vs. schematic] and [design rule check s]," said Magarshack. He also said that transistor density on chips is beginning to negatively impact timing.
"To increase quality and close the design gap, we also need to elevate the level of abstraction through the system level," said Magarshack.
Simplex Solutions' president and chief operating officer Aki Fujimura, known for his management of tool development divisions, called for improvements in software.
"Great companies produce quality software on time, but somehow magically we forget how to do quality software on time," said Fujimura. "It just isn't enough to have quality people."
Indeed, Fujimura pointed to a graph that showed that the more architects you have, the more likely you will have problems and miss deadlines.
"We have an illusion in software development that the software prototype is close to your production software," said Fujimura. "In other fields like automotive, you create a prototype or concept car and know it is not going to be the end product. In software we d o make that assumption. You think the prototype is 90 percent of the product, when in reality it is only 10 percent of the end product."
Fujimura also explained how, unlike the hardware design world where deadlines are fairly firm, software development deadlines are rarely firm. "If someone is late in getting their part of the project done, a software manager says, 'great, that means I have more time to add new functionality or firm up dirty code,' and then he or she sets a new milestone," said Fujimura. That, according to Fujimura, inevitably leads to more complications, more dirty code, the setting of new new milestones and the eventual release of a poor product.
"It is 20 times more costly to release a product with bugs," said Fujimura. "Releasing bad software can make you suffer for the rest of your life," he said.
To stop that cycle, Fujimura advocates setting "must," "should" and "could" goals for the different members of a tool development group. Under this approach, developers are give n tasks they "must" finish far ahead of the milestone date. Extra features for a tool "should" be finished just prior to the milestone or release date. Meanwhile, "could" features are set for after milestone dates have passed. Tool developers tackle them only if the rest of the tool development program is ahead of schedule, and the must and should goals have been completed.
LogicVision president and chief executive officer Vinod Agarwal argued that use of an embedded test strategy leads to embedded quality.
In his presentation, Agarwal noted that from 1998 to 2003 the percentage of designers doing 2-million-plus gate designs will have increased from 4 percent to 38 percent proliferating and complicating IC and thus system testing. Meanwhile, Agarwal also showed a Dataquest graph that predicted that the cost of test equipment will reach 15 million by 2009. "Testing a chip will soon cost the same as making it," said Agarwal.
To cut down on the costs of test while easing test complexity, Aga rwal suggested designers employ embedded test early in the design.
"If you take a chip with the ability to self-test or validate or verify, it becomes part of the chip's functionality," said Agarwal, pointing out advantages in the areas of IC development, test equipment costs and system development.
Those advantages include support for hierarchical design methodologies, automated embedded test generation, the ability to reduce or free up engineering resources down the road, and the ability to enable at-speed testing and diagnostics.
"Testing and diagnosing problems like bit mismatches can take seconds rather than weeks or even months," said Agarwal.
In addition, Agarwal said the embedded test methodology can be extended to all devices residing on a system pc-board to speed system development
Agarwal also spoke about the advantage of chips employing embedded test to tell customers and vendors when problems or potential problems are occurring.