English
32-Bit RISC-V Embedded Processor and Subsystem, Maps ARM M-0 to M-4. Optimal PPA,
Extreme Design: Realizing a single-chip CMOS 56 Gs/s ADC for 100 Gbps Ethernet
Ian Dedic, Fujitsu Microelectronics
8/25/2010 7:38 AM EDT
To provide a long-haul, 100-Gbps, optical transport network with maximum reach and immunity to optical fiber non-idealities, the industry has settled on dual-polarization quadrature phase-shift keying (DP-QPSK) as a modulation method, which means that a coherent receiver is required. The biggest implementation challenge resulting from this decision is the need for low-power ultra-high-speed ADCs, and their technology requirements define the way that such a receiver can be implemented.
A 100-Gbps coherent receiver needs four 56-Gs/s analog/digital converters (ADCs) and a tera-OPS DSP which dissipate only tens of watts. This paper discusses the forces pushing towards a single-chip CMOS solution, and the challenges in realizing this.
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