Microcontroller designers eye Internet access
By Bernard Cole, EE Times
April 6, 2001 (2:06 p.m. EST)
When 8- and 16-bit microcontroller companies spot the opportunities that exist in the emerging net-centric computing-device and embedded Internet market, they sometimes act like deer caught in the headlights of an oncoming truck.
The fast-approaching vehicle is, of course, the ubiquitous connectivity that the Internet and World Wide Web have created. Microcontroller companies are faced with only a few options: Focus on traditional embedded markets, shift to a more net-centric focus or find some middle ground and try to avoid getting hit by the truck.
| Software designer Nick Kelsey and architect Kintue Szeto are pushing for unprecedented speeds with Ubicom's Internet controller: 100 MHz, allowing for 100-Mips throughput. The iP2002 makes its debut at ESC this week. |
If they shift to a more net-centric focus, they can hop on the vehicle and participate in even more market opportunities. But that requires fast footwork, taking time that a market operating on "Internet time" will not give them if they stick to traditional strategies. Some of the microcontroller company strategies are on stage at the Embedded Systems Conference in San Francisco this week. All are designed to accommodate the ubiquitous connectivity of even deeply embedded microcontrollers.
Ubicom Inc. will showcase its embedded Internet controller and the associated software that supports it. Microchip Technology Corp. is sticking to its strengths in traditional architectures, but adapting to the Internet through strategic relations with software providers such as Live Devices Ltd. and CMX Systems Inc. Hyundai Electronics America Inc. is showing an 8-bit TCP/IP protocol-stack processor. Meanwhile, Lantronix Inc., a provider of co ntrol network solutions, is introducing a 16-bit network connectivity controller of its own design.
Tired of waiting for microcontroller vendors to make a concrete commitment to the new net-centric embedded environment, Lantronix (Irvine, Calif.), took control by designing its own Device Server Technology Network Interface (DSTni) chip.
This product signals the company's move from builder of communications subsystems based on microcontrollers to provider of a unique chip-level solution, containing all of the essential hardware components for enabling network connectivity. The chip will allow devices to be remotely monitored and controlled over the Internet or over shared networks.
"We've leveraged our 11 years of networking experience and engineering expertise to bring a full-featured network-enabling chip to market," said Rich Obermeyer, vice president of engineering at Lantronix. "We have tried to provide a microcontroller solution with all of the peripheral functions needed for many control applications but for the variety of networking options available."
Built around a 96-MHz 16-bit 80286 processor core, the DSTni chip incorporates two 10/100 Ethernet media-access controllers and an integrated physical-layer device. Additional interfaces include four high-speed serial ports, CANbus, USB, SPI, I2C and parallel I/O. The software kit includes a general-purpose real-time operating system, a TCP/IP protocol stack, a Web server and a complete set of C libraries and sample source code, developed by the company's general-purpose embedded-software subsidiary, U.S. Software Corp.
New name, new approach
Ubicom (Mountain View, Calif.) has thrown indecision aside and climbed onto the oncoming Internet connectivity bandwagon. Previously, the company added hardware functionality and software modules to adapt its earlier standard microcontrollers to net-centric applications.
Now, Ubicom has not only changed its name from Scenix, but adopted a new market focus and product thrust to reflect that change. It's produced a family of Internet-ready 8- and 16-bit controllers, the iP2000, with significant architectural enhancements that reflect their use in net-centric control applications.
The first part in this family, being demonstrated at the Embedded Systems Conference, is the iP2022. Fabricated in an advanced 0.25-micron process, the iP2022 is, like its predecessors, a 16-bit Harvard-style RISC-based deterministic architecture. But it operates at an unprecedented 100 MHz, allowing throughput of 100 Mips, with most instructions executing in a single 10-nanosecond clock cycle and a fixed, deterministic three-cycle interrupt response time. Speed impact
| Ubicom's Bulent Celebi says Internet-based design dictates a software ap proach to microcontroller peripherals. |
"When the company was first formed, the central differentiating idea we had was to focus on boosting microcontroller clock rates to as fast as the process technology would allow," said Bulent Celebi, chief executive officer and president. The higher speed then allowed Ubicom engineers to leverage the difference of the requirements of the application and the excess speed of the microcontroller to implement software-based virtual peripherals for additional functionality.
"That allowed us to build a broad application base very fast," Celebi explained, "because we or the customer could create the peripheral functionality in software quickly in months, rather than wait tens of months or several years until an 8- or 16-bit microcontroller emerged with the right features."
About a year ago, the company introduced its first Internet and communications-oriented software module for use with its microcontroll ers: SXstack, a TCP/IP stack for what the company was calling the embedded Internet.
In the home networking area alone over the next few years, said Celebi, there will be 30 million home LANs installed. Bridging from one protocol to another will create a large market in the home where a number of local protocols will be competing and coexisting, including HomeRF, Powerline, Bluetooth, 802.11, Home Pna, Havi and 1394. "Who knows which will win?" he said. "But one thing is certain: many of them will be coexisting for some time to come.
What Ubicom is finding, said Celebi, is that unlike traditional users of microcontrollers who were accustomed to working on design cycles counted in years, the new players in the embedded Internet device market really value a software-based approach.
According to Kinyue Szeto, iP2022 chief architect, new features have been added to the company's Harvard-based 16-bit architecture to support its new mission. To allow the developer to implemen t functionality and protocols in software that were not possible before, the device's program and data storage were doubled to 32k of 16-bit flash program memory and 8k of 16-bit RAM program/data memory. The second was to shift to a new process technology, which enabled the company to double the performance of the architecture to 100 MHz, allowing sufficient performance overhead to handle both the control and sophisticated communications functions. "With the exception of jumps and branches, all instructions on the new architecture execute in one cycle at 100 Mips," Szeto said.
Another feature of the new architecture is the addition of a phase-locked loop and clock circuitry, with a 2-MHz external clock, which is then multiplied up to the internal rate of 100 MHz.
Other improvements reduce power consumption but without sacrificing the 24/7 instant-on deterministic response that the new net-centric computing devices will require. "One of the criticisms of our earlier devices was that" . . . "they were power-hungry compared to standard microcontrollers," said Szeto.
To resolve that, Ubicom has developed a way to change the clock rate of the processor under software control, but without sacrificing determinism. This was done through the addition of a new SPEED instruction.
"Suppose the embedded device is in a quiescent state and everything is powered down waiting for an external event to happen," said Nick Kelsey, software design engineer. As soon as that happens, the device can, within two clock cycles, go from zero to 100 Mips, execute the operation at that high rate and then, under software control, ratchet down the speed to 50 Mips and then lower down to zero, or ramp back up. "Very few controllers have this degree of control," Kelsey said. "But by using the run-time variable-speed instruction, this becomes a relatively mundane task."
The SPEED instruction also specifies the clock source (OSC1 clock, RTCLK oscill ator, or PLL clock multiplier), and whether to disable the OSC1 clock oscillator or the PLL. The SPEED instruction executes using the current clock divisor.
Coupled with the new instruction is a redesign of the four- stage pipelines that are tightly coupled to the on-chip power management circuitry.
"We have a number of states inside the machine that allow us to perform certain power-down and power-up operations in a guaranteed and predictable fashion," said Szeto. "In a sense we have implemented a deterministic power-down mode. If you want absolutely the lowest power you turn off the primary oscillator and the phase-locked loop. But at power-up, in the highly deterministic environment the iP2000 will be operating in, we guarantee an absolute turn-on time at each step."
So, in a particular situation, the system designer will know exactly how much time it will take to go from 0 to 100 Mips or any range in between. This requires that the pipeline, the clocking circui try and the instruction sequence operate in a tightly coupled manner. Interrelated to the speed change capability is a similar control over the interrupt response .
To allow users to take advantage of the additional memory and the ability of the software to operate at the 100-MHz clock rate, Ubicom has also developed an extensive array of software add-ons called ipModules. These are software implementations of an interface, protocol or other function that replaces traditional hardware. The ipOS, to be introduced for the first time at ESC, is a small, spare, real-time deterministic operating system.