Vigraham Saranyan, Qualcomm
9/17/2010 4:05 AM EDT
Behavioral modeling has caught on quite fast in the analog verification community. A RTL like description on analog, RF and mixed-signal blocks has opened up more possibilities of thorough top-level verification for these cores. Now, the power and finesse of digital verification is being brought into the analog domain with the aid of improved modeling and test bench methodologies that are influenced by the “digital way” of doing verification. This influence has been both a help and hindrance to analog verification.
First things first, digital verification is much more advanced and time-tested than the more recent analog verification idea. The digital design methodology of RTL, equivalence checking and formal methods compliment the verification processes beautifully and everything fits in. Most often, the digital design engineers double up their role as verification engineers and run extensive test cases on their designs. I strongly believe that this strong bonding between digital design and verification makes the process work smooth. Analog verification is a different beast. The designers and verification engineers don’t play well together, mostly because of incompatible methodology issues. While the analog verification camp is beginning to believe that digital verification methodologies have to be adapted (like monitors, assertions and test benches), they are involuntarily alienating analog designers, who are not concerned about these aspects of verification. Analog design engineers are super-smart, keen and intuitive. However, most of the time, they are engrossed in the performance of their own designs. They don’t worry about the integration issues that their block/module might face with a digital core or other analog cores. They offload that worry to module/integration leads, which I believe is not necessarily the right thing to do. While a verification engineer worries about capturing the connectivity and functionality issues pertaining to the whole chip, design engineers worry about the performance of their blocks. On the other hand, the analog verification engineers these days don’t have an appreciation for analog design. There is a chasm between what they think analog design is and what it really is. Because of this lack of understanding/appreciation, there are communication issues between the modeling/verification teams and design teams.
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