SANTA CLARA, Calif. System-on-chip design is as simple as pc-board design; C and C++ are viable hardware design languages; and reconfigurable computing will replace ASICs these were among the seven myths panelists attempted to dispel last week at the IP/SoC 2001 conference and exhibition.
Dataquest Inc. chief EDA analyst Gary Smith, who moderated the panel of users and analysts, hammered on two myths: that "patents encourage technical innovation," and that "design-cycle times are shrinking." Smith said the electronics industry has become too serious about enforcing patents, and has thus stifled innovation.
"In the '80s it used to be that most of these disputes were settled quickly and quietly behind the scenes and only went to trial if it was a completely blatant ripoff," said Smith. "That just isn't the case any longer."
Companies these days must worry that their new product innovations may violate patents they didn't know w ere held by other electronics companies or, worse, by law firms waiting to sue patent violators, Smith said.
Smith also took aim at the notion that design cycle times are shrinking. He displayed a Dataquest chart which showed that design cycle times for all sectors except for automotive electronics have stayed level over the last five years at nine months to one year.
Steve Schulz, co-chairman of Accellera and CAD strategy manager for Texas Instruments Inc., tackled the "myth" that C/C++ will be the next hardware design language. Schulz concluded that a small group of individuals will always use unadulterated C/C++ for design, but that this total number will likely remain the same as it is today.
"C's notion of concurrency is to display two 'wait' dialog boxes at the same time," said Schulz, in a rapid-fire tongue-in-cheek presentation. "I predict C will be as popular for hardware design as it was 20 years ago when we decided to create HDLs."
Design consultant Paul Weil took on the myth that "SoCs are simple just like putting together a pc-board. "Managers wanted to believe that it would be simple: mark up a design on paper, get some parts, hook them up, run tests, fix any problems and you are done," said Weil. "It just isn't nearly that simple."
Rather, great tools and talented hardware engineers are required to complete an SoC design, Weil said. "There is this idea that SoC design is so easy that a system designer, a cheaper designer, can do it. That isn't the case," he said.
One problem of SoC design is the notion of mixing and matching intellectual property cores, Weil said. This conflicts with the 'I can do it better' credo of hardware engineers, who would rather design blocks themselves and quickly glue them together, much like a pc-board designer routes devices on a board.
EDN's EDA and technology editor Gabe Moretti grappled with the questionable notion that reconfigurable computing will replace ASICs. Moretti pointed out that the ASIC market is not likely to cannibalize profitable businesses and that ASICs' versatile size, package, performance, power and price advantages will allow the ASIC business to survive into the foreseeable future.
"Electronic design is not like sex," said Moretti. "Size does count, speed is desirable, power consumed is relevant, new markets are ethical and good, and cost must decrease with volume."
Ron Wilson, an EE Times columnist and the publisher of Integrated System Design, dispelled the myth that mask charges are increasing so rapidly as to price players out of the market.
To quickly dispel what he termed "[Gary] Smith's myths," Wilson presented two contradictory tables from Dataquest Inc.
One table, commonly cited in what Wilson termed "doomsday stories," showed mask prices rising dramatically for every shrink in process geometry. The graph showed the mask price jump from $250,000 for a 0.18-micron process to $300,000 for 0.13-micron process.
Then Wilson quickly showed a second graph, also created by Dataquest, which showed that the mask cost per gates is shrinking, from $0.013 per gate at 0.18 micron to $0.008 per gate at 0.13 micron.
"Huge costs will only be to baselines," said Wilson, who pointed to practices like the use of FPGA prototypes instead of masks and the use of multidesign mask sets and said they will ensure that mask costs won't make the semiconductor sector implode, at least any time soon.
Dataquest senior technical software analyst Laurie Balch tackled the last myth addressed by the panel that Web-based design is the wave of the future. Balch pointed out several myths perpetuated by vendors: that the Internet will increase the size of the user market; the Internet will eliminate costs of sales; Internet technologies are fully mature; Internet adoption is complete; and infinite, high-capacity bandwidth is pervasive.
Customers also perpetuate myths, Balch said, including the idea that everything on the Internet is cheap or f ree; the Internet will reduce cost of materials (assuming the absence of taxes on Net-based purchases); and that Internet technologies are fully mature and push-button.
"The new myth is that the Internet has failed," said Balch. "This is not true and there will be several opportunities." Balch said the Internet has truly aided engineers in communication, downloading up-to-date data books and evaluating IP.
"I also think small companies and design houses are good targets for Internet tools," said Balch, who concluded that it is still too early in the adoption cycle to count out companies trying to use Internet to improve engineers' lives.