SANTA CLARA, Calif. Faced with skeptical customers and weak sales, several intellectual-property vendors are calling for a major shift in their business model.
While most of the industry now functions at the register-transfer level (RTL), which allows for the easy transport of semiconductor designs in a digital format, some providers and customers are suggesting a migration to the electronic-systems level, where intellectual-property (IP) designs can be fully verified, making them a more convincing and more valuable alternative for customers afraid of bugs.
"We need a paradigm shift," said Joseph Rothman, president and chief executive officer of design and simulation tool vendor CARDtools Systems Corp. (San Jose, Calif.), during a panel discussion at the Intellectual Property/System-on-Chip 2001 (IP/SoC) show here this week.
Such a shift in the IP business model may be the only way to keep the industry afloat. "There is no viable RT L market for IP," said Gary Smith, chief analyst for EDA at market research company Dataquest (San Jose, Calif.). "There just is no business."
Star vendors like MIPS Technologies Inc. and ARC Cores, both of which sell microprocessor cores, already use this approach, Smith said. "IP that is designed in at the RTL stage is not successful. To be successful, it has to be designed in at the system level," he said.
The current business model has IP vendors selling a design based on a simple description of its function, and delivering the product as an RTL file. Since many of the designs have flaws, and many more require modifications to fit into customers' platforms, Rothman of CARDtools said this method is not the best way to allow potential customers to evaluate the IP blocks.
Instead, he suggested that the intellectual-property designs be taken to a more advanced stage of production, the electronic-system level, which will allow the cores to be run through full simulation and verification steps. "W e must move IP to a higher level," he said. "This will make it much more accessible to our customers."
Speaking at the same panel, Amr Mohsen, chairman, president and chief executive of Aptix Corp. (San Jose), said that if IP designs could be verified, it would be easier for customers to find the best blocks for their unique needs. "As anybody who has ever used IP can tell you, even if a block has been verified, it can still cause system-level problems," Moshen said. "It's very important to make the validation process as easy as possible."
Mohsen suggested creating an online database of cores, including both their specific functions and verification data, which users could download and plug into their own chip designs. "This way the customer can verify the IP in his own designs before he buys it," Moshen said. "This will accelerate the deployment of IP into the marketplace."
Steve Shulz, worldwide ASIC and CAD strategy manager for Texas Instruments Inc. (Dallas), said that his company has spent s o much time evaluating purchased IP cores that he has concluded it would be a better use of engineering hours to develop the blocks in-house.
"For the standard, jelly-bean types of IP, we've looked at the cost-benefit trade-offs, and they usually don't favor using external IP," Shulz said.
Though the model shift will require much more effort on the part of the vendors, Dataquest analyst Smith said it also makes their products more valuable and justifies a higher price tag. He predicted that selling preverified IP blocks could increase their value as much as tenfold.
Smaller product pool
A secondary consequence of this paradigm shift will become evident in the number of products available. Initially, requiring vendors to perform the extra steps of verification will lead to a smaller pool of products, as the designers will only work on cores that they know will sell. But after the new business model takes hold, Smith said, the extra revenues will permit vendors to begin offering m ore and more products.
"It will lead to an explosion of designs in the marketplace," he said.