Gaurang Kavaiya, PSoC Applications Director, Cypress
EETimes (10/3/2010 12:48 AM EDT)
Millions of instructions per second doesn't always represent the true computational capability of a device. Here’s what you can do about it.
It is common to represent microcontroller (MCU) computation capability in terms of MIPS (millions of instructions per second). However, no two MCU or system on chip (SoC) architectures are same, nor is the amount of integration to accelerate performance of various applications. Therefore, firmware applications may take fewer CPU cycles if proper hardware features are used. While migrating to different architecture, if developers rely solely upon MIPS to predict the computational capability needed for an application, they can be grossly mislead. This article analyzes various architectural features of MCU/ SoC in the context of some typical computational problems with the goal of exploring why MIPS doesn't represent the true computational capability of a device and what to do about this. Specifically, it will focus on MCU/SoC devices running at under 100 MHz as there aren't many benchmarking standards that focus on comparing system-level capability of these devices.
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