In recent years programmable-logic devices have found homes in applications ranging from high-performance wired products, such as DSL access multiplexers (DSLAMs), to the emerging 3G wireless formats. One reason for the underlying success of PLDs in signal-processing applications has been the availability of various DSP intellectual-property (IP) cores for programmable logic. Such cores let users exercise the full flexibility of PLDs while obtaining hardware-based performance.
Engineers have the option of implementing their designs either in software running on DSPs or in hardware (ASICs, application-specific standard products or PLDs).
Processors have been the traditional choice of many designers for signal-processing applications. DSPs are relatively cheap and flexible to use, and a broad base of third-party software developers has facilitated the processors' use . Most of the designers using DSPs are software engineers who progra m in C or assembly language to implement the desired functionality.
ASSPs and ASICs provide improved performance at a relatively low cost, which makes it very attractive for the designers to use them. Also, there are higher perceived reliability factors when it comes to ASSPs, which are specifically designed for a fixed functionality. With ASICs, designers can implement a customizable and low-cost solution.Performance benefits
Programmable logic offers compelling advantages over DSPs. Programmable-logic devices can be thought of as an array of elements, each of which can be configured as a complex processor routine. The processor routines can be then strung together in serial (the same way as a DSP would execute them), or they can be connected in parallel. In parallel they offer greater performance than a DSP by executing hundreds of instructions at once. Algorithms that especially benefit from this type of performance increase include forward error correction, modulation and demodulat ion, and encryption.
Programmable logic offers inherent advantages over ASSPs and ASICs in wireless communications. First, PLDs are more flexible, easing the modifications of coding methods and improving algorithms. This is especially true in emerging 3G wireless applications, such as IMT-2000 and W-CDMA, where the standards are constantly evolving, making PLDs an ideal platform for design implementation. Second, the performance and density of PLDs align optimally with wireless communication designs, where speed and time-to-market are of the essence.
Combining programmable logic with a broad portfolio of easy-to-use, parameterizable, high-performance DSP IP cores makes it even more compelling for designers to go down the programmable path. The IP here comprises ready-made, pretested functions that augment existing hardware-description language (HDL) design methodologies. The functions allow designers to focus more time and energy on improving and differentiating their system-level products, rathe r than on redesigning common off-shelf functions.
A comprehensive portfolio of standard DSP functions can be combined to form an entire system-on-programmable-chip, or DSP IP cores can be leveraged individually to improve systems requiring focused performance enhancements. With the performance advantages of parallel processing, coupled with the traditional flexibility of programmable logic, DSP IP is ideal for such emerging applications as 3G wireless, digital audio and video broadcast, multichannel multipoint distribution services (MMDS) and orthogonal frequency-division multiplexing (OFDM) systems. Designers can quickly adapt to such new standards as Wireless 802.11a, Wireless Broadband Working Group 802.16 and HiperLAN/2.
The first decision communications system engineers face when starting a new design is the trade-off between data reliability and data throughput. Using modern forward error correction techniques, receivers can correct the data, which may be corrupted during transmission, and increase the effective data bandwidth. Forward error correction (FEC) lets the receiver correct errors automatically without requesting retransmission. It is widely used in real-time systems for the transmission of audio and video data.
FEC is still based on adding redundant parity information to the data being transmitted, but in this case the receiver not only detects that an error has occurred but also calculates what information the transmitter is most likely to have transmitted. The two most popular forms of coding for error correction are convolutional codes and Reed-Solomon codes. Convolutional codes are commonly decoded using the Viterbi algorithm, hence the frequent use of the term Viterbi decoder. Another type of convolutional coding is turbo coding, which has gained a considerable amount of popularity and is increasingly being used in emerging 3G applications.
Reed-Solomon is an advanced error correction technique widely used in data communications, storage and mobile computing . It is based on a block-coding scheme wherein the input data is broken up into equally sized blocks, and each block's data is transmitted together with its parity.
Implementing Reed-Solomon on DSPs is expensive and is unsuitable for high-performance applications. But because of its parallel-processing-based architecture, programmable logic is an ideal fit for Reed-Solomon encoders and decoders. Designing a Reed-Solomon (RS) decoder is quite complicated; the designer must juggle multiple parameters. The myriad standards to be dealt with, each with its own set of requirements, further complicates RS decoder design.
Some IP vendors thus have created user-configurable IP, which allows the user to select the various parameters. For example, the Altera RS compiler supports three different architectures-discrete, streaming and continuous-to let the user make trade-offs between speed and area. Performance of the Altera Reed-Solomon encoder and decoder is heavily dependent on its parameters; but the encoder is capable of running at speeds well over 1 Gbit/second, and the decoder is capable of running at speeds well over 800 Mbits/s.
Viterbi decoding, or convolutional decoding, as it is better known, is another type of forward error correction algorithm. Viterbi decoders are difficult to implement, since the designer must consider a variety of parameters. They include the number of coded bits, traceback length, constraint length, number of soft decision bits, precision of branch metric accumulation, polynomial of each coded bits and puncturing rates.
Viterbi decoders are usually implemented on DSPs and ASSPs, but with the increased availability of high-performance Viterbi decoder IP, PLDs now can outperform DSPs and ASSPs. Altera's Viterbi compiler IP is highly parameterizable and supports all the various parameters mentioned above. It provides a maximum throughput of more than 100 Mbits/s (compared with maximum throughput of 1 Mbit/s for a typical DSP).
But performance is not t he only concern. In many instances, the user must make a trade-off between speed and area. For example, some satellite communication applications require a throughput of only 30 Mbits/s but need a cost-effective solution. In such a scenario, the price of the solution is more important than the performance.
Viterbi compilers like Altera's let the user trade off between speed and area in designing the appropriate Viterbi decoder. The user has the option of selecting among three architectures-high-speed parallel, low-speed serial and medium-speed hybrid-to achieve the desired performance and size.
With the compiler, the high-speed parallel architecture uses a pure-logic implementation and runs at well over 100 Mbits/s but consumes the most logic elements. It supports puncturing rates from 2/3 to 7/8. The Low-speed serial Viterbi decoder is configured on a memory-based architecture, has a typical performance of 0.5 to 3 Mbits/s and consumes the least number of logic elements. The medium-speed hyb rid Viterbi decoder has a typical performance of 1 to 7 Mbits/s, and its size varies between those of the high-speed and low-speed Viterbi decoders.
Turbo coding, or iterative coding, has gained considerable momentum in the past year. It is a combination of iterative "soft-in/soft-out" decoders with simple component codes and an interleaver that has further narrowed the gap to the theoretical limit (or Shannon limit). Turbo coding as specified by the Third Generation Partnership Project (3GPP) is primarily used in 3G applications and involves the use of two convolutional encoders: one applied directly to the data and the other to an interleaved version of the data. Turbo decoding is iterative, and each iteration consists of decoding each convolutional code in turn. The chosen decoding method must have "soft output," since each decoding operation updates the likelihood of each received data bit's being a logic one or logic zero.
Turbo coding is complex to implement on any platform, and the sta ndards continue to evolve, making it even more difficult to implement in an ASSP or ASIC. DSP processors don't have enough Mips to compute this mathematically intensive algorithm. Since the standard for turbo coding continues to change, programmable logic is an ideal platform to implement the algorithm. To address the increasing number of opportunities in 3G applications, Altera has successfully implemented the turbo encoder and decoder at data rates in excess of 2 Mbits/s as specified by 3GPP.
The turbo decoder features a max-logMAP algorithm for maximum error correction and includes a 3GPP-compliant interleaver.
Interleaving is frequently used in communication systems to improve the performance of error correction schemes by mitigating the effects of burst noise. Interleaving is the reordering of symbols in a data stream. When used with Reed-Solomon coding schemes, it ensures that adjacent symbols being transmitted are from different code words. Many communications channels are subject to b urst noise, either from interference from extraneous sources or from variations in the channel characteristics over time. Time efficiency
Designing modulators/demodulators to such formats as m-QAM, MPSK and DPSK could become an easy matter if users have access to numerically controlled oscillators, FIR filters, and symbol mapper/demapper functions. Those functions are not as complex as some of the FEC functions but are still time-consuming to develop.
Numerically controlled oscillators can be designed with DSPs, ASSPs or programmable logic. DSPs use a lookup table with interpolation to generate a precision sinusoid using limited on-chip SRAM. ASSPs give higher performance than DSPs, but with fixed angular/magnitude precision. On the other hand, PLDs provide complete solutions with high throughput and the flexibility of user-defined angular/magnitude precision.
Programmable logic is also better-suited than DSPs for filtering applications. DSPs have a limited number of MACs and requi re many clock cycles to compute each output value. A dedicated hardware solution can achieve one output per clock cycle. A fully parallel, pipelined FIR filter implemented in a PLD can operate at data rates over 100 Msamples/s.
Having a variety of DSP IP cores will not be the only solution for the next generation of designs. PLD vendors will need to provide a seamless tool flow between the hardware world, using HDLs, and software world, using C or assembly languages. The combination of a broad portfolio of DSP IP cores and the integration of third-party DSP system-level tools will put programmable logic in the forefront of signal-processing applications.