Developers of wireless LAN products must perform a high-wire act. On the one hand, high spectrum utilization is very important because of the shared multiple-access nature of the channel and the ever-increasing demand for the limited spectrum, which requires more complex modulation schemes and sophisticated transceivers with high-performance processing requirements. But on the other hand, low-power solutions are particularly important for mobile terminals, and low-cost ones are particularly important for user terminals. So developers have to balance these objectives, choosing among ASIC chip sets, discrete (off-the-shelf) DSP chips and DSP core-based system-on-chip (SoC) for wireless LANs (WLANs).
An ASIC chip set generally provides higher performance and uses less power than a DSP-based solution. However, the problem with the ASIC approach is the myriad, fast-changing nature of standards for wireless LANs. For example, after the appear ance of IEEE 802.11 in 1997, which provided a data rate of 2 Mbits/second, IEEE 802.11b appeared in 1999 supporting data rates up to 11 Mbits/s. Then in 1999 IEEE 802.11a was standardized with a maximum data rate of 54 Mbits/s.
Further, many product vendors provide proprietary solutions with higher data rate options while supporting the existing standards. The fundamental modulation schemes used for the physical layer for each standard can be different as well. For example, 802.11 uses Direct Sequence Spread Spectrum (DSSS) technology, whereas the 5.5-Mbit/s and 11 Mbit/s access rates of 802.11b use complementary code keying (if the optional convolutional encoding is not employed), and 802.11a uses Orthogonal Frequency Division Multiplexing (OFDM). DSSS requires many operations that work at the bit level while OFDM demands many complex-valued multiplications. Another important standard is the emerging IEEE 802.16 for wireless broadband access; there is also the idea of using IEEE 1394b for wireles s connections in the home. Obviously, a single implementation that accommodates the multiple wireless LAN physical layers must be extremely flexible.
The DSP alternative
An alternative approach to wireless LAN development is the DSP-based approach. It relies on a programmable DSP to perform most functions in the transceiver with, possibly, fixed-function accelerators for certain operations. In addition to its flexibility for various wireless LAN standards, a DSP-based solution potentially allows for future multimedia products, which support more than one standard-for example, an MPEG decoder may be downloaded for a video application. Additionally, getting to market quickly is essential in these products, making a DSP-based answer more desirable. Also important is the lower risk factor associated with programmable DSP-based solutions where some discovered problems may be fixed in software.
Within the DSP-based approach there are two alternatives. The first is the off-th e-shelf DSP chip solution, and the second is the purchase or, more commonly, licensing of a DSP core to be integrated with other functional blocks on one chip (see figure).
The off-the-shelf way is easier where the product development team lacks sufficient SoC design experience. However, that approach generally has higher power dissipation and higher costs associated with it relative to a comparable integrated DSP core-based solution. Another important advantage of the integrated or SoC approach is configurability. This gives the product developer the option to tailor the DSP core to particular applications. For example, the data memory, instruction memory and, if available, very long instruction word memory sizes are typically custom-sized. More significantly, DSP cores may have a base instruction set, such as the BOPS ManArray architecture, from which they generate different cores with instruction sets that are subsets of the base architecture. This type of semicustom approach eliminates unneede d functionality, reducing product cost. Additionally, some op code space is left unused for special application-specific instructions.
What makes such semitailored instruction set architecture desirable is that many applications require a specific set of operations that are not needed in other applications, in addition to the core set of operations common to most DSP applications. This implies that with SoCs more interaction is required between the product developer and the DSP core provider. Indeed, DSP core providers offer greater flexibility than traditional DSP component vendors, especially for a fully integrated SoC solution. In particular, DSP core providers offer licensing rights to their core intellectual property for integration into an SoC as well as development tools and application software to help complete the system solution. All the above, coupled with the elegance and smaller footprint of an SoC solution, make a compelling argument to use integ rated DSP core-based SoC.
In addition to those design considerations, wireless data communication places particular requirements on the DSP. The fading nature of the wireless channel implies the need for channel correction at the receiver. The high peak-to-average power ratio (PAPR) of OFDM symbols makes the design of linear and inexpensive amplifier stages difficult, prompting the use of PAPR-reduction algorithms. Various solutions have been devised for these two problems and they generally involve many complex multiply operations, which must be performed quickly on all samples of the OFDM symbol. For example, in IEEE 802.11a there are 64 samples per OFDM symbol with a duration of 4 microseconds. This implies the need for parallelism in DSP solutions for wireless LANs.
One solution is BOPS' Manta chip. It contains four processing elements that can simultaneously operate on different subsections of input data in a single-instruction, multiple-data fashion. This parallel clustered archit ecture leads to almost no interprocessor communication overhead, resulting in cycle count reduction factors that are in many cases approximately equal to the number of processing elements. Packed data is another level of parallelism that allows the processing of multiple data elements in a single instruction. The data element size may be a byte, half-word (16 bits), word, or double-word (for which register pair processing is utilized). This kind of increased parallelism allows a lower overall clock rate for a given application compared to standard DSP architectures. On the other hand, increasing the clock speed to provide the necessary processing power results in higher power dissipation that is undesirable for wireless data applications as mentioned earlier.
Some operations remain difficult to perform on any DSP; in this case a fixed-function accelerator integrated with the SoC would improve performance considerably. For example, the interleaver and deinterleaver, which are required in the 802.11 a standard, involve many bit-level manipulations for which DSPs are generally not very well suited.
Other important considerations in the choice of a DSP are the development tools that accompany it.
A good set of tools includes an easy-to-use GUI-based software development kit and a powerful debugger (that can handle multiprocessors in the integrated SoC case) customized for the specific architecture. Finally, evaluation boards and software as well as training and engineering support are critical to timely product development.
Where possible, DSP core-based SoC solutions appear to be the most suitable for wireless data communications applications. Powerful DSP parallelism is another important feature for wireless data processing that is preferable to increasing the DSP clock speed to obtain the processing power requirements of wireless data applications.
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