Shiv Sikand, IC Manage
EETimes (10/22/2010 12:02 PM EDT)
Nearly half (47 percent) of IC design engineering and CAD management indicated that design data management issues had caused design and tapeout delays for their organizations. The average delay cited was almost 3 workweeks (14 days).
This is one of the findings of a blind, worldwide survey of 426 IC design professionals on Global SoC Design Management. The majority of the respondents (53 percent) held engineering and CAD management positions. The remaining respondents included digital, full custom and FPGA designers (32 percent), verification engineers (8 percent), and software and firmware developers (7 percent).
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