Panel concurs: Designers must deliver complete solutions

Panel concurs: Designers must deliver complete solutions
By Michael Santarini, EE Times
February 6, 2001 (2:23 p.m. EST)
URL: http://www.eetimes.com/story/OEG20010206S0061

SAN JOSE, Calif. — Designers who aim to increase the efficiency of system-on-chip (SoC) devices must develop complete design-closure solutions by addressing timing, signal integrity and power concurrently. That was the overriding message delivered by speakers at the Design Closure Seminar held last week.

Keynote speaker Vinod Dham, father of Intel's Pentium and now vice president and general manager of the carrier access group at Broadcom, said that while many tools are maturing to help designers deal more effectively with timing closure, there are many other issues such as signal integrity and power that also delay design closure.

"When we were creating the 486, we worried about capacitance; when we created the Pentium, the problem was resistance and capacitance; now there are things to worry about that we never dreamed would arise, especially in the areas of noise, process and power."

At the Feb . 1 seminar, Dham presented an EDA wish list calling for better tool interoperability; tools that enforce correct-by-construction, system-level design tools; tools geared toward low-power design; and overall productivity improvements.

In a user panel hosted by Integrated System Design editor Peggy Aycinena, users from Broadcom, C-Cube Micro, Fujitsu, NEC, Silicon Access Networks and Sun Microsystems presented wish lists similar to Dham's.

All of the panelists recently taped out multimillion-gate SoCs implemented in 180-nanometer processes or below, and most were eyeing projects implemented in 130-nm processes.

Reza Hariri, director of ASIC design at Silicon Access Networks, called for tools to have better silicon-to-gates timing correlation, more intuitive signal-integrity analysis and better power and clock distribution.

Sun Microsystems engineering manager Willis Hendley asked for hierarchical design-planning tools that can handle a large number of top-level blocks; tools that have n oise avoidance, detection and repair features. He also requested tools that facilitate top-level assembly, addressing complex I/O structures and metallization.

Hooman Moshar, director of engineering for the Residential Broadband group at Broadcom, looked for signal-integrity tools that address inductance as well as resistance and capacitance. Inductance occurs when switching signals interfere not only with the net next door, but also with nets farther away and perhaps on other layers.

Saeid Moshkelani, C-Cube's vice president of operations and core technology, said even today's cutting-edge physical synthesis tools, which link synthesis and place and route, still require wire load models. Moshkelani said he would like to see synthesis and place and route more closely linked and would like to see top-level wire load analyses for module-level synthesis.

Moshkelani also wishes for power-savvy place and route tools that would allow for power tapering.

Panelist Tetsu Tanizawa, manager of advance d design methodology at Fujitsu Microelectronics, said that he would like to have tools that better manage signal flow starting at floor planning.

He said that current routers and buffer insertion tools do not interact effectively to lessen RC effects. Tanizawa also called for power and noise estimation to begin during RT floor planning, and requested tools that allow groups to design clock and power buses concurrently.

NEC's Kazu Yamada said he would like to see better timing-closure tools with automated rules of thumb and reduced design variables for routing.

Yamada said his group is working on three designs in 130-nm technology and that these designs in particular require extensive noise and electromigration analysis. He would like to see tools that address antennae effects across multiple layers as well as tools that account for hot electron effects via wire load models.

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