SoC peripheral model makes dual run
By Kevin Donovan, Product Marketing Manager, Large Systems Technology Group, Synopsys Inc., Beaverton, Ore., EE Times
December 22, 2000 (3:32 p.m. EST)
With complex embed-ded-system designs exceeding 1 million gates, verification has become the critical bottleneck in the design process. To improve time-to-market, embedded-system designers have turned to a hardware/software co-verification methodology. Traditional co-verification models often sacrifice accuracy and completeness for performance. This trade-off becomes a huge problem for complex processors with multiple embedded peripherals because a major part of the system software interacts with the peripheral hardware.
Until now, no one has devised a satisfactory approach for modeling these extremely challenging systems. However, the pressure is mounting for a comprehensive modeling solution because those systems are being deployed more extensively in high-profile tele-communication applications such as wireline, wireless and satellite switching stations.
The core processor itself in those communication systems is fairly straightf orward to simulate. What makes it so complex is the surrounding circuitry. The peripheral circuitry typically includes one or more of the following: Ethernet ports, bidirectional serial ports, PCI bus interface, LCD screen driver and SAR I/O, among others. With all that functionality (which tends to be highly configurable), there are thousands of different setups and states that need to be examined to fully exercise and verify systems using the devices.
Over the years, several companies have attempted to create a comprehensive simulation environment for the devices, including their peripheral blocks, but could not overcome the sheer complexity of the systems. Consequently, the available models were either considerably inaccurate or incomplete. Hardware emulation, such as in-circuit emulation, is another alternative, but the designer loses critical visibility of the flow of software through the core with that approach. Plus, emulators have extremely limited throughput, hampering the overall verificati on effort.
Recognizing the need for a more comprehensive modeling approach for these complex communication systems, Synopsys Inc. has created an innovative solution that combines the accuracy of hardware modeling with the speed and visibility of software simulation. The unique approach models the processor core using an ISS (instruction set simulator) in place of the actual silicon core. This gives software developers and hardware designers a clear view into the execution of code running on the core. Then a hardware modeler is used with the ISS to precisely model the detailed activity of the device's peripheral circuitry.
This technology, which combines an ISS and hardware modeling into one co-verification environment, is extremely flexible to ensure highly efficient design verification. For example, the instruction-set simulator can be "decoupled" from the hardwa re simulator when running source code on the core. The ISS can then be recoupled to the hardware simulator on the fly when the software developer or the hardware designer wants to scrutinize the interactions between software execution, the peripheral circuitry of the device and the rest of the customer's design.
With its unique combination of hardware modeler and software simulator, this modeling environment creates a powerful, realistic modeling solution for devices with complex peripherals. Now both hardware and software designers can move their challenging designs to market much faster. Having complete visibility into the entire system's operation considerably improves the ability to debug complex application code much faster. The capability of modeling the device's complex peripherals with 100 percent accuracy greatly improves the chance of first-pass success. This technology can be applied across most embedded processors with complex peripherals available today.
Modeling a complex microc ontroller, with enough speed to support comprehensive verification of large amounts of application code and complete functional accuracy, has not been accomplished before with an accurate software model. Writing a software model of this type of device is extremely expensive and time-consuming. History has shown it to be impossible to get a 100 percent accurate model with useful simulation performance using software modeling techniques alone, including encrypted register-transfer level. Testing the model to ensure its correctness is an even more daunting task. The device itself is its own best model. The hardware model alone is fully accurate, but it's not fast enough for hardware/software co-verification, nor does it provide the observability and controllability of software execution as does an ISS.
This new technology combines an ISS, modeling the embedded processor's CPU core, with a hardware model, which models the complex peripherals. The ISS and hardware model are linked through the Synopsys Eag le VSP Library and a special Synopsys Eagle bus-functional model (BFM).
The BFM, hardware model and an initialization memory model are in Verilog or VHDL, which are executed by the simulator. The ISS is written in C, and is linked to the BFM.
Application software is executed by the ISS, at an average speed of at least 100,000 instructions per second, when it is uncoupled. The ISS software can execute either coupled or uncoupled from the hardware simulation.
New technology from Synopsys, called CrossLink, delivers the desired combination of software execution speed, hard-ware accuracy and simulation performance that software developers and hardware designers require.