Logic suppliers seek ways to embed FPGAs in SoC
Logic suppliers seek ways to embed FPGAs in SoC
By Yankin Tanurhan, EE Times
December 22, 2000 (3:28 p.m. EST)
All logic suppliers, driven by the economics of integration, are moving toward system-on-chip (SoC) devices. As the design and mask set costs of these devices skyrocket, however, system OEMs are struggling with the complexities of meeting market demands.
In parallel with this, available time-to-market is shrinking, and the resulting delayed product entry cuts into market share, revenue and profit.
Driven by the convergence of communications, computing and consumer applications, product life cycles are sometimes shrinking to as little as six months. Adversely, SoC design complexity increases the time required to bring competitive products to market, putting a premium on design speed and flexibility.
In this environment, it is no wonder that standard FPGA products are enjoying great success for a numbe r of reasons. FPGAs have always been able to help reduce development cycles, development costs and, thus, time-to-market. Its comparative process disparities with ASICs have been reduced as independent foundries adopt the reprogrammable static-RAM (SRAM) FPGA as a driver for their next-generation technologies. In addition, there has been a rise in the popularity of reconfigurable systems.
Engineers at Actel Corp. have developed a family of embedded, programmable SRAM-based gate array cores used in SoC devices that we are preparing for introduction next year. With this embedded programmable gate array (EPGA), we hope to offer the ASIC and application specific standard product (ASSP) design communities some alternatives.
The ability to add programmability to their products will relieve ASIC and ASSP providers from some or all of the challenges mentioned above. For example, in an ASIC or ASSP, Actel's EPGA in SoC silicon will play the role of "soft hardware" and, in essence, transform the SoC wo rld for the next level of reconfigurability.
Being late to market puts a huge cost opportunity at stake. However, the enabling technology is now available to embed core blocks containing programmable gate arrays in large ASICs and ASSPs. The result is a single device with the flexibility and time-to-market benefits of an FPGA and the dense integration and cost benefits of an SoC.
Embedding FPGA cores in SoC designs will address time-to-market and design risk issues by:
- Reducing development lead times and development costs;
- Avoiding increasingly costly mask set changes and silicon re-spins;
- Enabling platform-based design;
- Permitting designers to rapidly and inexpensively adapt to changing standards or add market-specific or application-specific function blocks;
- Allowing the verification of hardware and software in parallel with manufacturing and qualification;
- Allowing the design of multiple products using one mask set;
- Permitting placement of riskie r design elements in the EPGA, delaying decisions on some functions until the end of design;
- Extending product life by adding the ability to change product features or functions during production phase;
- Permitting higher profitability of integrating high-margin standard FPGA functionality into lower-margin standard cell silicon.
When programmability is added to ASICs and ASSPs, the economics of reconfigurable solutions are changed. FPGA technology brought together with ASICs through a common methodology addresses the needs of the embedded market of SoCs: logic, DSP, reprogrammability and nonvolatility. Specialized architectures now can be provided for prominent applications as well as for compatibility with cell-based SoC tools, BIST (built-in self test), interface and JTAG.
The goal of any embedded programmable solution is to maximize performance and minimize power and die area in the SoC environment. But even if these difficult-to-achieve objectives are realized, embedded progra mmable logic IP will never attain success unless the methodology used for its design, verification and integration with ASICs or ASSPs is synergistic and seamless with today's standard SoC design flow.
To ensure success, a level of compatibility needs to be set for these new EPGA cores with existing standard SoC flows, logic synthesis, and the tools used for verification and test.
Actel has an embedded core methodology that employs parallel design flows for hard-IP integration and soft-IP design. In this flow, front-end register-transfer-level (RTL) code gets synthesized, using standard ASIC synthesis (Verilog or VHDL) tools, into a netlist representing the soft IP. A proprietary place-and-route engine then maps the resulting design netlist to an EPGA netlist and generates a configuration bit stream for the embedded-logic core. From the place-and-route netlist, a delay calculator computes routing delays, which are then exported as an SDF file to timing-analysis or simulation tools.
Fo r its EPGAs, Actel has combined the capabilities of timing-driven design, block-based design and design reuse to form a hierarchical platform-based design methodology. Using predictable, preverified logic blocks with standardized interfaces increases design productivity.
Platform-based design methodology separates the design into distinct areas: block authoring and system integration at the silicon level. The objective is to create a highly productive architecture that extensively employs fewer edits to functional blocks and uses planned design reuse to maximize improvements in time-to-market.
The integration of a reprogrammable, configurable "soft hardware" solution in the form of an EPGA helps designers maximize the potential of platform-based design using only a single mask set.
Depending on the perspective of the system architect, be it platform designer, platform-based designer or system-OEM designer, the approach and importance of manufacture, core interface, core function and hardware diagnostic problems will be quite different. Verification solutions will need to be equally effective in serving each of these criteria.
For the platform designer, manufacture and core interface problems are most critical, with some attention being devoted to core functions. IP reuse and the approach to new designs are other important considerations. Hardware and software programmability in the system also is going to grab some of the designer's attention.
On the other hand, platform-based designers will focus almost all of their attention on EPGA core functions, take some note of the core interfaces and virtually ignore manufacturing and hardware diagnostics. Platform-based designers' priorities are retargeting the platform for other applications and adding new functionality. Hardware diagnostics get the lion's share of the system-OEM end users' attention with some notice given to EPGA functions. End users look for the capability to customize the platfor m, change features or field-update programmability on varying applications.
During partitioning of the EPGA within the design, the functional blocks in the system need to be identified and their interaction with each other examined. An estimate of cost functions (area and performance) must be weighed against flexibility and variants before valid block-partitioning decisions can be made. Once these blocks have been identified and valued, the design can be partitioned.
YANKIN TANURHAN IS DIRECTOR OF EMBEDDED FPGA AT ACTEL CORP. (SUNNYVALE, CALIF.).
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