Greg Hackney, Fedor Pikus, Mentor Graphics; Steven Chen, M.J. Huang, TSMC
EETimes 11/17/2010 3:21 AM EST
Increasing numbers of integrated circuits (ICs) are targeted at mobile/wireless applications. The amount of analog content in these designs increases as designers integrate more functions such as WiFi, Bluetooth, 3G, GPS, and audio. The difficulty of verifying these designs is compounded by the fact that the chip designer may be including analog IP from outside sources. The chip designer might not have any analog background. This situation requires fast, robust, automatic verification of analog design rules. Traditional methods of verification are inefficient and error-prone.
Special needs for analog circuits
Analog circuits have a number of special requirements. A simple example is matched devices. Analog circuits rely on matched devices having the same electrical characteristics within a very tight tolerance. This requires a lot more than matching transistor widths and lengths. To minimize manufacturing variances, matching devices must be laid out close together. The devices must also be placed symmetrically and in a similar local environment to avoid imbalanced lithographic distortions and directional manufacturing process differences.
Proximity and symmetry can be checked with a traditional DRC tool, but how can a designer recognize which devices to apply the checks to? Designers use marker layers to identify circuitry that require special rules but marker layers have several deficiencies.
First, and most obviously, marker layers can be misapplied. An analog device without an analog marking layer will not be properly checked. Also, it is very easy to mistakenly place marker layers over circuitry that should not have them. Second, marker layers do not have enough information to allow sophisticated checks: they indicate only that a particular device must be matched to some other device, but not to which one.
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