It may prove to be an overstatement, but reprogrammable and reconfigurable architectures, com-
monly known as ASIPs (application-specific instruction processors), are poised to become the next big craze in the system-design world. With advances in new ultradeep submicron process technologies, designers have more gates at their disposal than ever before-and, many argue, more gates than they can possibly fill, given today's tool/design methods and time constraints.
As process geometries have dropped during the past five years and gate counts have risen well into the millions, the EDA, semiconductor and systems industries have tried to plot new ways to allow hardware designers to efficiently and effectively use all the gates afforded to them. But with Moore's Law raising the bar in terms of silicon gate counts, the efforts much resemble Sisyphus' futile task of pushing the bolder to the top of the hill only to have it roll to the botto m every time it reaches the crest.
About five years ago, when process geometries were poised to drop below 0.5-micron and the million-gate design came into view, the industry stepped up efforts to form internal groups and consortiums to enable designers to mix and match various cores, typically in sizes of 2,000 to 50,000 gates, to create system-on-a-chip (SoC) designs.
Designers soon discovered, though, that mixing and matching IP was more complicated than they originally thought it would be; numerous integration, verification and legal/licensing issues still remained to be ironed out.
At the same time, Moore's Law kept raising the bar, and 0.35-, 0.25- and 0.18-micron processes started to make million gates available, taxing the capacity limits of traditional ASIC tools and requiring greater numbers of hardware designers to complete projects.
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|By making platforms either reprogrammable or reconfigurable, University of California's (Berkeley) Kurt Keutzer expects to see application-specifi-instruction processors steal business from the ASIC and programmable logic markets. |
In light of this, the design industries started thinking in terms of SoC platforms-an evolutionary step above core-based design, in which several commonly used cores like MPUs and DSPs are premixed and matched and preverified to create a platform or macrocore in the range of hundreds of thousands of gates.
These standard platforms targeted for particular applications can be mixed and matched or have cores added to them to create systems-on-chip. The design task, however, still requires large hardware design groups, taxes current tool suites and does not adequately address time-to-market pressures to the satisfaction of many systems companies, esp ecially those in the dot-com sector.
At the same time, the mask sets for these ultradeep submicron chips are creeping toward the million-dollar mark and ASIC design starts are shrinking.
To address most of these problems, a new effort in the form of ASIPs is just now pushing its way through the academic arena on its way to the design industry. ASIPs promise to make platforms either reprogrammable or reconfigurable, so that software designers can design/program silicon. This, proponents said, will relieve the designer shortage, open semiconductor silicon to a larger design audience and remove much of the time crunch because platforms are preverified and can be quickly configured and programmed.
Cary Ussery, president and CEO of Improv Systems Inc. (Beverly, Mass.), said reconfigurable architectures, which can be dynamically reconfigured in the field to create mass customized products, also promise to expand the lifetime of a systems company's product: As new standards and features are required, systems companies can simply reconfigure the silicon to change with the times. This may spell trouble for the semiconductor industry in terms of design starts, but it also has the potential to save design houses and system companies expensive mask sets, respins and overall silicon costs.
Enthusiastic ASIP proponents, such as the University of California's (Berkeley) Kurt Keutzer, professor of electrical engineering, say application-specific instruction processors may steal business from the traditional ASIC and programmable logic markets.
"I have spent an inordinate amount of time over the last 10 years trying to figure out what's next-and I think these ASIPs are going to take away a lot of the traditional ASIC business," said Keutzer, who is leading the Gigascale Silicon Research Center's efforts on researching ASIP architectures through the Mescal networking architecture. "I think this is going to be one of those exciting things that comes around only once in a deca de."
Other industry observers, such as Gary Smith, chief EDA analyst at Dataquest Inc. (San Jose, Calif.), are more cautious, noting there are still many issues to be resolved, especially in terms of tools and skill sets.
In this week's focus on tools for reprogrammable/reconfigurable architectures, we hear about the Mescal project in a contribution penned by Keutzer and several of his researcher colleagues at U.C. Berkeley.
From the looks of it, the shift to ASIP has already taken hold. Established silicon vendors such as Actel, Altera, Lucent and Xilinx are announcing products in this area, and a new breed of fabless/IP companies such as Adaptive Silicon, BroadCom's Silicon Spice, Chameleon Systems Technology, Improv Systems, MorphICs, PMC's Malleable Technologies and Quicksilver, are offering or preparing new ASIPs.
In the section, contributions from Altera and Xilinx detail their aggressive moves into the ASIP world while new vendors such as Improv Systems and Adaptiv e Silicon discuss the methodologies that are needed for ASIP design.
Ravi Subramanian, vice pres-ident of systems architectures at MorphICs, said ASIPs come mainly from four types of companies: programmable logic vendors offering standard cell/programmable hybrid devices; ASIC vendors offering parameterizable data paths; DSP vendors, like TI and the DSP Group, offering reconfigurable arithmetic; and microprocessor core vendors, such as ARC Cores, Tensilica, and Intel, offering reconfigurable control. ARC Cores and Tensilica discuss their architectures and how they are used later in the section.
According to Keutzer, vendors that currently offer or are planning to offer ASIP products have their own tool suite and skill-set design requirements. Over time, however, that should change-methodologies and tools, he said, will consolidate to create a tools industry that is different from the EDA industry as we know it.
"There are really two problems in an ASIC: One is building it and the other is programming it," Keutzer said. "I would say that the major EDA companies are focused on building it."
Keutzer said ASIP designers will work with a new generation of compilation and estimation tools, such as compilers, performance-analysis tools, instruction set simulators and debuggers.
He predicted that these ASIP tools will evolve in much the same manner as ASIC tools, first being provided by the silicon or IP vendors that create the ASIPs and then, after a period of architecture consolidation, offered by third-party vendors. Reforming designers
"The customers programming these chips will be reformed ASIC designers, software developers who understand concurrency and system designers," Keutzer said. "The key to providing a successful software development environment will be to present the application developer with a programmer's model of the device that will allow them to exploit all that concurrency. Until we get that problem licked I think we will see architectural and software development environment chaos."
Dataquest's Smith said another barrier blocking the success of ASIPs is a shortage of software engineers who understand concurrency. "It's a great idea to put a lot of the control in the software guys' hands, but there aren't a lot of software engineers out there who really understand concurrency," he said.
Smith believes that verification of large ASIPs is going to become a big issue. But he is optimistic that many of the issues centering on tools, methodologies and skill-set requirements will be resolved in time.