Panel ponders cost of programmable system-on-chip

Panel ponders cost of programmable system-on-chip
By Peter Clarke, EE Times
October 25, 2000 (10:42 a.m. EST)
URL: http://www.eetimes.com/story/OEG20001025S0003

EDINBURGH, Scotland — Adding programmable hardware to system-on-chip (SoC) devices is a little bit like the weather: Everyone talks about it but no one is doing anything about it, if discussions at the IP2000 Europe conference and exhibition are any indicator.

The anecdotal evidence presented at a lunchtime panel challenged with counting the cost of adding programmable hardware suggested there is much metaphorical "tire-kicking" of this design style and of the relatively few devices that now support it. But there is no strong trend toward using partial hardware programmability, according to panelists representing some of the more advanced proponents of these techniques — LSI Logic Corp. (Milpitas, Calif.), QuickLogic Corp. (Sunnyvale, Calif.) and Mentor Graphics Corp. (Wilsonville, Ore.).

Moderator Luke Collins, EDA and intellectual-property (IP) analyst at Dataquest Inc., set the scene by discussing some of the possible reasons to us e hardware programmability.

Collins pointed out its possibilities for reducing risk for ASIC developers by allowing them to correct for functional errors after production. He also spoke of the opportunity to use programmable technology to develop multiple-use or field-upgradable products.

Collins then pointed out some of the inhibitions, including the up-front cost of the technology for uncertain benefits later on, as well as verification uncertainties.

Hardware programmability can be achieved in a number of ways. In fact, in a sense it falls into a continuum of solutions extending from FPGA logic and metal-only respin of a gate array design, through setting memory values in registers, all the way up to entirely software solutions effected on processor hardware.

Collins asked the panelists to detail how to choose the appropriate solution and how to figure its cost.

Iain Jackson, director of marketing for LSI Logic Europe, made the case for a solution soon to be offered by his company &# 151; of a conventional ASIC design based on large, licensable IP blocks fully diffused in silicon but with areas of FPGA-style programmable logic.

Jackson observed that while hardware programmability allows flexibility and reuse, speeds time-to-market and lets multiple customers use a common architecture, it comes at the cost of integration, performance and power efficiency. A fully diffused design style can help solve all those problems, he maintained.

"SoC designers want hardware programmability but not a fully programmable solution," said Jackson, arguing that developers still want leading-edge integration, performance and power efficiency.

For Jackson the answer is straightforward: embed some field programmability but retain the advantages of the custom ASIC manufacturing style for most of the silicon die area. "At 0.18 micron and below, 50,000 gates of programmable logic adds less than 10 percent additional die area," Jackson said.

Thomas Oelsner, general manager for QuickLogic Europe, made a case for the standard FPGA product with one or two useful but highly desirable functions that can be produced in volume for multiple customers.

"We call it the embedded-system product; Dataquest terms it the application-specific programmable product, or ASPP," said Oelsner, whose company traditionally supplies FPGAs based on its antifuse technology.

Flexibility retained

Oelsner stressed that the trend toward higher gate counts, at least for random logic, was also tending toward custom solutions. He pointed out that this approach avoids the non-recurring engineering charges associated with ASIC development, coming to be dominated by mask charges, but retains the full flexibility of FPGAs as long as you want the predetermined function, be it a CPU core or PCI-bus controller logic.

It was left to David Wood, IP product marketing manager for Mentor Graphics, to analyze the situation in terms of EDA support and design methods.

Wood pointed out that with integration of CPU c ores on SoC devices becoming almost trivial, whether in ASIC or in FPGA, the frequency of software-only mediated reconfiguration was likely to increase. Nonetheless the difference in computational efficiency between software and hardware solutions makes the case for engineers who "choose to do things in software early on when standards are fluid and then commit to hardware when the standard firms up," he said.

Wood postulated the universal digital chip as a device with CPU and memory and a significant area of programmable logic. This combination, which he believes could soon arrive, would make it possible to swap functions from software running on the CPU and hardware-accelerated functions in the programmable logic. But Wood also said that such a chip would require a thorough understanding of constraints, appropriate libraries of IP and EDA support for appropriate what-if analysis.

"I might propose a new design gap," Wood said. "The ability to program this stuff is clearly there. It's a question of can you exploit it?"

Although the panelists were unable to put a dollar number on the cost of adding programmability to an SoC, their discussion did map out just how complex such a costing exercise would have to be.

In the audience discussion that followed, it became clear that one driver for adopting such methods lies in cases where there is a clear benefit to the chip user rather than the chip designer.

"Programmability does help engineers recover from mistakes, but field upgradability could be used to reduce replacement cost," said Jackson of LSI Logic. "Take the case of the 3G [third-generation communications] basestation. Once the network operators have deployed them they don't want to send the white van round to make a change."