Practical Case: Embedded Multiprocessor Design on a Flexible Hardware: NEO_CORE_CYCLONE_III

JOATTON Philibert, DECHANDON Thierry (ADENEO)

1. Goal and opportunities of a hardware reusable design

ADENEO’s customer needs, in Power Converting sector, are often similar. Differences are mainly focused on power gate driving, system interfaces and monitoring.
From this finding of similarity, it is obvious that generic development enables leverage across various designs, allowing us to focus on specific design related to customer needs

Considering High Power converter applications, ADENEO’s previous hard & soft design solutions had the following limitations:

• Too slow response time for safety aspects in the case of a single processor design.
• Increased Complexity in the case of a “processor + FPGA” Design
  • Higher Hardware Complexity (more complexity for board design)
  • Double design team because of the two components
• Non configurable external interfaces (too rigid for reuse)

Those thoughts led ADENEO to define a digital design reference that addresses most of the needs encountered on our various “Control & Command” projects.

Following requirements have been defined as guidelines for the new design:

• Maximize genericity of the digital core to let us use it in our various businesses: NEO_CORE concept.
• Need of high speed and determinist treatment for protection of equipment and people => FPGA needed
• Allow possibility of multiple CPU to support software processing load of application.
• Scalable CPU power (linked to running frequency) to adapt it to design complexity
• Development costs globalizing to increase competitiveness of our offer.
• Starting from a proven base to allow rapid focusing on customer specific needs and improve “time to market”
• Design the digital core (NEO_CORE_CYCL ONE_III) as a mezzanine to increase its reusability
• Enable density migration for cost optimization

These requirements led us to consider “System on Chip” as an attractive and effective answer:

• Reusability
• Maximum flexibility (FPGA)
• Scalable CPU processing power (working frequency and number of processor).
• Easy partitioning (and repartitioning) between VHDL and C design.
• Interconnected HW and SW development team

2. Hardware Reference Design: Architecture and key features

The generic hardware architecture developed by ADENEO is called NEO_CORE_CYCLONE_III. It is based on an ALTERA Cyclone III FPGA and SoC architecture.

This module has been designed to suit the current industrial requirements: reduced size (60x42 mm), low power consumption (below 2W) and harsh environment (wide temperature range from -40°C to +85°C).

NEO_CORE_CYCLONE_III board includes high performance devices:

• FPGA Cyclone 3 EP3C55F484I7N, containing 55k logic elements and 2340kbits of on-chip RAM memory and operating up to 200MHz,
• Up to 1Mo of 16-bit SRAM memory,
• Up to 64Mo of 32-bit SDRAM memory at 100 MHz,
• Up to 64Mo of NOR Flash at 40 MHz,
• PHY Ethernet 10/100 BASE-T

It also presents external interfaces such as digital I/Os (CAN and PC104 compliant), LVDS I/Os and Ethernet link.
Finally, the Cyclone III FPGA is perfectly suited as an embedded processor when combined with ALTERA's 32-bit Nios® II embedded processor intellectual property (IP) cores.

The possibility of implementing “Systems on Chip” (microprocessors + peripherals) actually helps the module to cover a wide range of applications.

3. Software Reference Design : Architecture and key features

3.1. VHDL SoC and IPs

As mentioned previously, the generic hardware offers the main following interfaces and peripherals:

• 64Mo of 32-bit SDRAM memory at 100 MHz,
• 64Mo of NOR Flash at 40 MHz,
• 1Mo of 16-bit SRAM memory,
• PHY Ethernet 10/100 BASE-T
• Multiple Digital IO for application

ADENEO FPGA Team has created a Reference Platform (Hardware BSP) that allows a NIOS processor to access to the NEO_CORE_CIII resources

Our platform was designed with ALTERA tools which allowed us to quickly build our System On Chip

The SoC platform was mainly composed by “off the shelf” IPs (short design cycle). Main design steps were:

• Design of VHDL custom IP (with AVALON interface)
• SoC creation under SOPC BUILDER (assembly and configuration of IP)
• Software development under NIOS IDE (small C routines to test SoC functionality).

• Memory test routines (GALPAT procedure)
• RTC tests
• UART transfers
• µC Linux port on NEOCORE used to test Ethernet IF

All these activities lead ADENEO to a proven hardware and SoC reference design.

3.2. Software architecture around NEO_CORE_CYCLONE_III

Considering the hardware design described above,
ADENEO’s Embedded Software Team has been working on a full custom configurable architecture, based on the following components:

• A bootloader for booting the platform
• A configurable Real Time Operating System for multi threaded applications running on the NIOSII
• Device drivers, and peripheral drivers for internal resources management
• Communication protocol over external link, for maintenance and supervision of embedded application
• Specific software Configuration Management rules

3.2.1. Real Time kernel or not ?

ADENEO can provide embedded and realtime software solutions to its customers.
Our proven technical expertise in embedded technologies makes software developers to be able to work with many multitasking, real time operating systems including Linux, eCos, µcOS/II, VxWorks, or FreeRTOS.

More precisely, it means that ADENEO has already been working with eCos, the open source and royalty-free embedded Configurable Operating System.

Since the port for NIOS II was available in eCos release, it has been an opportunity to re-use previous internal experience and an opportunity to take advantage of its configurability. Indeed, eCos can be wholly configured through a PC-based application called eCos Configuration Tool.

In the development planning phase, the Embedded Software Team performed the following activities :

• eCos BSP (Board Support Package) for NEO_CORE_CYCLONE_III support, as a new platform.

As an example, the Intel StrataFlash (NOR Flash) driver and the Ethernet driver were added to the BSP.

• eCos kernel configuration to match NEO_CORE_CYCLONE_III resources.
• TFS (for Tiny File System) package integration on Intel StrataFlash. This Flash File System allows real time application to consider the memory space allocated to flash to be treated as name space instead of address space. Moreover, TFS certainly makes the embedded system easier to manage (firmware update, multiple configuration file storage on target….)
• Unitary and integration testing, including measurement of eCos kernel performances around Interrupt latency.

Although eCos is currently the major real time kernel solution for NEO_CORE_CYCLONE_III board, other solutions can make the board to match specific customer’s requirements. A µCLinux port is available and OS-less applications have been developed to manage non-real-time systems.

3.2.2. Booting the platform

The NEO_CORE_CYCLONE_III board relies on the bootloader software to be present, in order to boot the platform, once the FPGA bootup procedure has completed.

The following requirements have been identified as guidelines for selecting the Bootloader :

• NIOS II core support
• Configurable bootscript, so that the system startup can be managed. Typical startup operations launched by a bootscript can consist in performing a memory self-test and then loading and transferring control to the application (and the operating system kernel).
• Execute-in-Place (XiP) capability
• TCP/IP and RS232 support, so that a command-line terminal allows remote system management
• File System Management capability, to perform easy file management

The bootloader Redboot has been identified as the best solution:

• based on eCos, it guarantees
  • consistency with the OS
  • Ecos NEO_CORE_CYCLONE_III BSP direct reuse (drivers)
• Configurability: same PC-based application as Ecos for configuration (eCos configuration Tool)
• Reduced memory footprint
• Execute-in-Place (XiP) capability
• TCP/IP support provided by eCos

3.2.3. Software Library

ADENEO Software Embedded Team has created a Reference Software Library that allows new application to take benefit of NEO_CORE_CYCLONE_III memory resources, real time resources, and generic VHDL Intellectual Properties (IP) cores resources.

The software library is divided into three parts:

• The first section being devoted to device drivers, boot management and real-time capabilities. The eCos BSP contains the several software components listed above.
• The second section being devoted to layer interface library for VHDL IP Cores dedicated to a specific industrial application (see § 4).
• The third section being devoted to an existing group of reusable embedded software components that provide interface for an external PC-based application, so that engineers and customers can monitor the embedded application at run-time. ADENEO has made the eCos / NIOS II port for these proprietary components that are OS-dependant and core-dependant.

3.2.4. Maintenance and supervision

Adeview© software is a PC-based application, specifically designed for observation, analysis, advanced troubleshooting of complex problems over embedded ADENEO’s software.

This performance monitoring tool grants read and writes access to the whole memory map of the NIOS II core, and thus allows software variables to be read and written at run-time.

Adeview© is able to connect to the embedded application through a RS232 serial link, Ethernet link or CAN bus link, with a unique and proprietary protocol. One can imagine easy Wireless possible using a GSM-GPRS modem connected to the NEO_CORE_CYCLONE_III.

ADENEO engineers consider Adeview© as a powerful and reusable unit testing tool around NEO_CORE_CYCLONE_III board. From a commercial point of view, ADENEO provides license to its customers to make them able to perform maintenance operations on their systems.
3.2.5. Configuration Management Rules
ADENEO’s Software developpement team uses SubVersion, the famous configuration management and version control system.

A unique SubVersion repository contains the whole generic source code as well as the whole application specific source code.

Configuration management rules have been defined for the NEO_CORE_CYCLONE_III SVN repository, in order to facilitate and ensure the maximum reuse of generic software modules.

Similarly, management of software defects (called modification management) is driven by rules known by software developers. Those rules enable impact analysis of bugs dealing with a generic software module, and the postponement of changes to other projects that include this module.

4. Focus: practical case

This practical case illustrates use of the NEOCORE_ CYCLONE_III in a typical railway power converting application.

The main features of that application are:

• 50 kVA Static Energy Converter composed of a DC chopper converter and a variable frequency three phases inverter.
• Final use in air conditioning systems in French suburban trainset.
• Input : : 400 V DC
• Output 380 V AC three phase voltage
• System communication on CAN interface

In this application, Hardware design is composed of a NEOCORE_CYCLONE_III digital core connected to a motherboard (called GECCO Board) that provides application interfaces (signal conditioning) to the NEO_CORE digital I/Os.

FPGA team built a dedicated System On Chip that meets the functional needs and provide enough CPU power for software processing tasks.

Thanks to the proven reference design approach, the SoC basis was available. FPGA Team had to add the specific blocks to handle converter control and CAN bus interface :

Starting from the SoC reference design, following blocks were added :

• A CAN bus controller IP (based on an OPENCORES Design) for network communication.
• Multiple SPI controllers for internal acquisition and generation
• A specifically designed library of VHDL and software IPs called COREG

Global SoC contains 3 NIOS processors. Main NIOS (NIOS of the reference design) handles global system supervision and communication.

Power converting control loops are handled by Secondary NIOS processors embedded in COREG IPs :

• DC chopper converter IP, corrected 3 PI control loops (9.6 KHz loop)
• Three phases inverter IP (5.4 KHz loop)

COREG is a library dedicated to control / command processing. It embeds VHDL code (interfaces, configurable IIR filters, fast protection for power elements, calibration, PWM) and Secondary NIOS processors
Secondary NIOS application is OS-less, and compiled with compiler optimization options, thus reducing memory foot print (10 ko). Application code is located in on-chip memory (M9K).

Secondary NIOS processors are inter-connected to the main NIOS through internal Avalon Bus, via a Memory Mapped Interface, and allows the whole COREG’s configuration (VHDL configuration registers and application parameters) to be set by the main NIOS application.

SoC architecture let us take the better of both worlds :

• On one side predictability and rapidity of VHDL for critical tasks and interfaces
• On the other side flexibility of C software.

5. Proven reusability of the concept

ADENEO is currently designing another system based on the NEOCORE_CYCLONE_III module

The customer need is to control embedded systems (locomotive) with a simple language (GRAFCET) with a high safety integrity level (SIL 2) design requirement.

To meet customer requirements, ADENEO has designed a racked system composed of:

• CPU board based on NEO_CORE_CYCLONE_III technology
• Digital and Analog IO boards

Main features are

• Data processing
  • ISaGRAF application – SIL Level 0
  • Safety function – SIL Level 2 – VHDL
• Communication interface
  • Ethernet network (3 M12 ports)
  • CAN 2.0B isolated port

NIOS processor run under eCos operating system and execute ISaGRAF software in order to execute customer’s GRAFCET.

The SoC architecture allows to mix on-chip :

• low Safety Integrity Level component : embedded firmware running ISaGRAF under eCos real-time kernel.
• high Safety Integrity Level function : VHDL specific IP with integrity control.

This segregation allowed us to only develop part of the VHDL design under SIL2 framework, and provide significant economic gain on NRC.

This successful project highlights the ease of reuse of the NEOCORE_CYCLONE_III HW and SW for various types of industrial application.