ASIC/SOC keynote addresses SoC in the Internet age
ASIC/SOC keynote addresses SoC in the Internet age
By Tets Maniwa, EEdesign
September 22, 2000 (12:28 p.m. EST)
Washington, D.C. - For the ASIC community, the future is the increasingly ubiquitous SoC, the system on a chip. That was the message in the nation's capital last week at the IEEE ASIC/SOC conference and the theme of keynoter John Kelly, IBM's senior vice president for microelectronics.Talking about communications in SoCs, Kelly said that because of the emphasis on the Internet's infrastructure more than 30 percent of new ASICs will have mixed-signal components on-chip. And the drive toward connectivity everywhere will make the PC market look small as the hunger for greater bandwidth is catered to by many companies, each with multiple architectures to handle network infrastructure.Kelly said that the move toward wireless and optical access platforms will increase demands for more storage and compute power in next-generation hardware. However, he added, even as manufacturers meet the requirements for increased performance, reliability, quality, bandwidth and throughput they will have to meet the requirement for lower cost. They must do all this, said Kelly, as convergence of voice and data cause the hardware platforms to look very much like mainframe computers, with the CPU driving very large memories and multiple I/O or network processors. All this has changed the definition of SoC. Originally, it meant some compute engine plus some memory and more than 150,000 gates of additional logic. But now the functions that comprise an SoC include at least one processor, multiple subsystems, SRAM, embedded DRAM and analog functions. Not only has the gate count and die area grown much larger, but also the complexity has increased tremendously. To deal with these SoC initiatives, ASIC vendors have made tremendous strides in the silicon technologies. Because network infrastructure applications need greater performance at lower power, they have gone to silicon on insulator, which has characteristics that provide up to 20 percent more performance and use 30 percent to 70 percent less power compared to standard CMOS. Look for SOI technologies to become pervasive in the next few years. In addition, other technologies like silicon germanium and integrated passive components can provide RF capabilities at a lower cost than the current leader, gallium arsenide. Still, the biggest problem facing the industry is the growing gap between processing capabilities and design tools. Commercial tools are capable of constructing and verifying designs of a few million gates, but silicon vendors can produce devices with more than 40 million gates. At the 180-nm process node, available tools are barely able to handle timing matters, so ASIC vendors are developing other in-house tools for specialized timing, testing, packaging and embedding memories. One alternative to the brute force design methodologies is to invoke a philosophy of massive design reuse. The highest level of reuse is to adopt a platform-based strategy that connects differentiating peripheral functions to the fixed design portions via an on-chip bus. By using a predefined platform, the design team starts from a previously synthesized, verified and integrated set of functions. The platform helps achieve first-time silicon by providing an emulation capability through bonded-out cores and extensive models. Other advantages of platform-based design include the reduction of overall design time and the ability to quickly construct an emulation system by developing the custom logic in an FPGA and connecting the core to the custom logic. The reduced ASIC design cycle also helps software development, as many working systems are readily available for software integration. The disadvantage of platform-based design is that the complete design infrastructure has to change to include earlier interactions between the hardware and software developers. In his keynote address, Kelly described a number of examples of this process based on IBM's customer experiences. A set-top box design went from four ASICs to one when the customer migrated t o a PowerPC-based platform with preverified cores and support functions. The inclusion of high-performance embedded DRAM on the chip increased the bandwidth and performance of the box while simultaneously reducing the pin count. In another design, a network processor, the customer was able to migrate the software functionality for an architecture with 20 picoprocessors to a platform-based solution by using high-level models and bonded-out cores. The use of an API reduced the port time to less than three months from more than 15 months for the code at the picoprocessor scale. As the processes and technologies change, he said the process module compatibility becomes an issue. SoC process complexity increases 20 percent to 30 percent for each additional technology. The result is lower yields, higher costs and more time to manufacturing maturity. Logic and DRAM are the most advanced processes, followed by Flash memories one process generation behind. Analog trails by two or more process additional generations . The ability to pack all the system functions into a single package rather than all on a single chip reduces the technology challenges. Kelly said that IBM can produce a stack of dice to allow process and technology selection to optimize the capabilities of a circuit. The base chip is designed so smaller circuits with functions in other technologies are attached with flip-chip technology. An alternative is to use multichip module technologies, which also allow mixed technologies and reduced external pin counts. As ASICs move toward SoCs, the engineering functions have to accommodate to the new environments, and ASIC vendors and design organizations must work with third-party partners. The software development has to accelerate to match the pace of the hardware developers, especially as platform-based designs dramatically reduce the silicon design cycles. Also, changes in processes and technologies require a constant upgrade of tools and methodologies to keep the tools current with the latest design option s and problems. The upshot is that design engineers don't have to worry about employment for the next 10 to 15 years. The demand for more engineers will outpace the supply even with the advent of accelerated design techniques like platform-based design.
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