A new approach to modem development separates the modem-specific software from the hardware and, therefore, has a profound impact on the platform design flow.
Pascal Herczog, Cognovo Ltd -- EDN, December 6, 2010
Cellular communication has evolved at an enormous rate in terms of both features and performance. From the inception of GSM, through multiband, GPRS, EDGE, and onto 3G UMTS, the silicon technology and design methodologies have struggled to stay ahead of the wave. This situation has led to a succession of architectures and long cycles of redesign.
Initially, the modem processing IC within the terminal consisted of both software-programmed DSPs (digital signal processors) and some hardware-centric elements to cope with high-speed data processing. However, with the advent of 3G release99, data-processing requirements for all parts of the modem became out of reach of standard DSP architectures, and the gap has widened ever since. Around 1.5 million gates of dedicated hardware logic plus associated memories were needed to implement the 3G rake receiver, combiner, and channel decoder, leaving the DSP to control the dedicated hardware and close the loop on algorithms such as multipath selection, AFC, and AGC.
The introduction of HSDPA, new equalizer designs, and parallel operation with release99 modes has required further increases in the amount of dedicated hardware, with typically another million gates and associated memories for category 10 HSDPA and more for HSUPA.
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