In the programmable-logic market, it's no longer enough to be bigger, faster, and cheaper than the next guy. To win -- and keep -- the hearts and minds of OEMs, PLD suppliers are shedding their dated "bucket of gates" image for a more sophisticated appearance that, not coincidentally, resembles a standard-cell ASIC.
Taking a giant leap forward in the evolution of PLDs, Altera Corp. today will begin offering what is viewed as the missing link in system-on-a-programmable-chip solutions: high-end microprocessors.
Altera has signed deals with ARM Ltd. and MIPS Technologies Inc. to embed versions of the ARM9 and 4K processor cores that have been optimized to work well in its APEX devices. Additionally, Altera is fielding a home-spun configurable RISC core, known as Nios, for applications that are less demanding in regard to performance.
The embedded-processor program, dubbed Excalibur, marks a turning point in the company's development, according to Cliff Tong, vice president of corporate marketing at Altera, San Jose. "We aren't abandoning our traditional business that brought us to $1 billion in revenue. But to become a $5 billion company, we think this approach is critical," Tong said.
Embedding processors in PLDs is an idea whose time has come, observers said. Altera rival Xilinx Inc. agrees and is working with a specific processor instruction set, but is not ready to discuss product plans, said Dennis Segers, senior vice president of FPGA development.
Appealing to low-end designs, meanwhile, are suppliers such as QuickLogic and Triscend, which are marketing configurable logic surrounding hard cores from MIPS and ARM, respectively.
While the solution will vary from supplier to supplier, one fundamental element is a proven and reliable PLD architecture. Motorola Inc. tried and failed a few years ago to embed the ColdFire processor in its Pilkington FPGAs, recalled Bryan Hoyer, Altera's senior director of system-level solutions in Sant a Cruz, Calif.
"What they found was that, even though Motorola has arguably the finest processor architecture in the world, when they went into the market with an untried, unfamiliar PLD architecture, there was a lot of push-back," Hoyer said.
PLDs today are dense enough and fast enough that it makes sense to hard-code certain system-level blocks, suppliers say. Newer device families feature embedded memory, clock management, and I/Os. Within a few years, PLDs are expected to integrate mixed-signal capability and high-speed communications interfaces.
The strategy has well served low-volume designs that can't support the exorbitant cost of ASIC mask sets. However, suppliers draw the line at fixing functions that would limit a chip's use to a narrow customer base.
"There's been a gradual evolution taking place ... to be more tuned for various application segments, but PLDs will generally remain generic from customer to customer," Xilinx's Segers said.
While the inclusion of a processor does not signal a major shift in the basic character of PLDs, Segers said, "when you start to talk about integration of a microprocessor and PLD, ultimately the direction that needs to be pursued is one of performance synergy. That implies a level of coupling between the processor and PLD that you wouldn't be able to achieve with two chips."
With embedded processors in the bucket, Altera believes the traditional market for PLDs can be expanded to encompass designs that today are done with standard-cell ASICs, ASSPs, and stand-alone processors -- a market that is forecast to exceed $50 billion in 2003.
Today, that collective space is being served by chip makers who "aren't going to move over easily," Hoyer admitted. Thus Altera has drawn a road map to 64-bit processors and tools, real-time operating systems, and an expanded IP portfolio geared toward communications.
The company has dedicated 13% of its gross revenue to research and development this year, and efforts over the last 18 months have been s pecifically in this area, Tong said. Currently, more than 150 software engineers are developing tools worldwide, three dedicated IC-design teams are working on a hard-core initiative, and more than a dozen people are working on Nios, according to the company.
Market watchers said Altera was wise to tie down agreements with both of the leading embedded-processor suppliers, not only for the broad base of potential design wins, but also for the existing support in the way of development tools and infrastructure.
For OEMs, the deals mean they won't have to negotiate a license or royalties with ARM and MIPS, a process that can be costly in both time and money, noted Tom Halfhill, an analyst at MicroDesign Resources in Sunnyvale, Calif.
The jury's still out on whether an embedded approach will enable PLDs to finally crack the high-volume business suppliers covet, said Bryan Lewis of Dataquest Inc., San Jose.
"This will open up the market for the smaller-volume guys, but will large OEMs start using it as an ASIC alternative? That all depends on the cost structure," Lewis said. "A programmable part gives you flexibility, but at what cost?"
Altera hasn't released pricing for the ARM and MIPS products yet, but is targeting a volume price of $5 for the Nios core, in addition to the price of APEX silicon ($39 in volume for 200,000 gates).
The configurable core is designed to deliver 50-mips performance on a 16/32-bit data path. The 16-bit RISC-based instruction set features a five-stage pipeline architecture that delivers one instruction per clock and supports parallel processing in a single chip, according to Altera. The core consumes 25,000 system gates-roughly 12% of an APEX EP20K200E, or 2% of an APEX EP20K1500E.
While it's geared for use with the APEX family as a delivery vehicle, the Nios core can easily be retargeted at low-cost designs based on Altera's smaller ACEX parts, the company said.
To jump-start designs, Altera is offering a bundled development kit for $995 that includes th e Nios RISC CPU, Quartus software, and Cygnus GNUPro development tools, along with peripherals, a reference design, and a development board with download cable.
Altera's ARM and MIPS offering will initially consist of 133-, 166-, and 200-MHz speed grades, and cores will include standard peripherals such as UARTs and timers. The cores are being hardened to Altera's 0.18-micron process, and are being manufactured by Taiwan Semiconductor Manufacturing Co. Ltd.
ARM- and MIPS-based devices are expected to be available in the fourth quarter of this year.
Additional reporting by Mark Hachman