Dimensionless notation is saving area and power in numerous analog designs.
Fortunately, the era of asynchronous digital subscriber lines (ADSL) is upon us, resolving for many the tedium of sharing the phone line with the Internet access line. In the Pairgain microelectronics group (The microelectronics group for Pairgain Technologies, Inc. based in Tustin, CA, has recently been acquired by Globespan Semiconductor, Inc., of Red Bank, NJ.), the analog methodology we are using has produced significant savings in both power and area for our ADSL chip designs. Our methodology allows us to port chip designs directly to a selection of foundries and across a variety of feature sizes. The company is currently porting its ADSLII AFE chip from a 0.35-µm to a 0.18-µm basic feature size. Because process line widths typically scale down by a linear factor of 0.8 per generation, we are achieving area savings of more than 50 percent.
Designers capture circuit schematics using a dimensionless notation that can be applied to any process technology line width. The resulting circuits are viable over several process generations without wasting layout time or redrawing all of the basic cells. Subsequently, using this method, Pairgain has saved over a year of layout time on the company's latest ADSL analog-front-end (AFE) chip.
The basic flow used in the methodology begins with the capture of circuit schematics using Viewlogic's (Marlboro, MA) View Draw. Rather than use conventional dimensions, designers specify polygon sizes in increments of 1/4 of the standard feature size. This standard feature size, F, represents the minimum gate length for a given process. Designers may also add various device attributes to the schematic so that the View Draw netlister output processes and inputs to Viewlogic's View Analog simulator. By providing process-specific parameters in separate technology files, Pairgain can use Vie w Analog to simulate a circuit and see its performance for any required processes. Designers then base layouts on a set of portable layout design rules (PLDR), applicable to any foundry or line width.
Starting with the basics
While universal design rules have been widely used for digital chips, such rules have seldom been used for analog circuit layout. However, the pressure to scale analog circuits along with digital logic in mixed-signal devices such as Pairgain's ADSL chips has prompted the company to give high priority to process portability at the beginning of the design cycle.
In order to scale down analog MOS devices, you have to deal with some basic issues. For example, optimum device current density (µA/square) doesn't change significantly from one foundry to another or as you change line widths. Liberal use of current-mirror biasing can assure that current densities track in all devices within the circuit block. When operated at the same current density, however, scaled-down de vices require less gate drive (Vg-Vt). Therefore, device transconductance improves slightly at constant-current density with scaling, while device capacitance decreases.
Figure 1 - Analog MOS layout options
The three basic layout shapes for analog MOS devices showing different combinations of shared, unshared, and cascoded sources and drains.
There are two things that help decrease excess phase-shift from parasitic amplifier poles: high-device transconductance and reduced device capacitance. Reduced excess phase leads to increased stability. Over a wide temperature range, bias control that is proportional to absolute temperature reduces gain-bandwidth variations. When used with increased bias currents, these combinati ons result in higher amplifier-gain bandwidths with scaling.
Additionally, electric fields within the device increase at constant voltage as you scale down line-widths. Therefore, this requires some reduction in individual device operating voltages. High vertical-fields at the gate-drain can result in reduced-output resistance due to impact ionization-effects.
High vertical-fields from gate to substrate can result in gate oxide time-dependent dielectric breakdown (TDDB). Power levels from 5 to 5.5 megavolts/cm have long been considered acceptable to achieve low gate-oxide TDDB. With gate-oxide thickness below 40 angstroms at 0.18µm-line widths, however, preliminary TDDB test results indicate that it may be acceptable to increase gate-oxide fields to 6 megavolts/cm in some processes.
Cascoding techniques have long been used to reduce operating voltage, decrease Miller capacitance, and increase output resistance. By cascoding, circuit topologies can preserve good a nalog signal headroom. In switch applications where thickness reduction results in unacceptably high gate-oxide field strengths, you can easily shift the switch-thin-oxide layer to a thicker layer. Most foundries provide a second thin-oxide layer at line widths of 0.35 µm and smaller.
Analog MOS design has become easier since the introduction of the first mixed-signal processes, which just added a precise capacitor to a standard digital process. Newer mixed-signal processes include a 200 to 300 ohms/square polysilicon resistor and zero-threshold MOS devices. Zero threshold input devices and differential-pair devices increase headroom within bias devices and permit wider input-signal swings when supply voltages are scaled down.
Sidebar - Dimensionless analog schematic
The circuit represented by the schematic is a classic folded cascode-transconductance amplifier. As drawn, the amplifier uses zero-threshold PNP devices in the input differential pair. The attributes TP0 4F M2 for devices P1 and P2 designate a zero-threshold device model TP0, a width of 4F, and a multiple of two devices with no shared drain. You can use any arbitrary variable X, for example to carry the model, W/L, source/drain configuration, and device multiple (M) designation. Just add the X attribute to the MOS device attribute list in the View Draw schematic as:
On the other hand, reducing thresholds doesn't reduce device saturation voltage-important in limiting output-voltage swing. Additionally, the short-channel performance of zero-threshold devices usually isn't as good as the normal Vt devices and the additional mask steps needed to make the devices increase the wafer price.
It's possible to eliminate the requirement for zero-threshold devices by increasing analog supply voltages more than the digital supply. Using this approach, Pairgain analog design doesn't require zero-threshold devices. Note that the scaling technique described here doesn't apply to pads because assembly equipment limitations don't permit pad-pitch to scale as fast as silicon feature size. Working around this limitation by oversizing the pad-pitch for initial designs allows pads to be used over more than one process generation.
One of the most critical device conditions to monitor when scaling analog circuits is the difference between each device's drain-source voltage (Vds) and its saturation voltage (Vdsat)-a difference defined as the drain-source voltage headroom (VHRM). To remain in the saturated region of operation, the instantaneous Vds must always be greater than the instantaneous Vdsat. In other words, the headroom must always be greater than zero to maintain the device in saturation.
As you scale down power supply voltages, headroom margins decrease by design. Therefore, it's important to check the headroom operating conditions for all devices over the full dynamic range at critical combinations: input signal frequency, dynamic range, supply voltage, and temperature and device speed. While several performance characteristics such as power supply rejection ratio (PSRR) and time response are indirect indicators of headroom problems, direct measurements are always useful.
A key to designing scalable a nalog circuits is the use of dimensionless layout. Silicon compiler work done by Carver Mead at the California Institute of Technology more than two decades ago led to the widespread use of universal rules for digital circuit design. A dimensionless parameter, l, was defined as equal to one half the basic feature size, or minimum gate length.
The Pairgain design methodology uses F units to obtain similar scalability for analog circuits. F corresponds to the basic feature size, or minimum gate length. To achieve high lithographic density, layout units as small as one-quarter of the basic feature size are permitted.
A grid size of 1 µm is convenient for ease of layout, and then you draw the basic feature size F at 4 µm, with 1 µm being the smallest layout unit. That arrangement allows you to develop the PLDR rule set in 1 µm units. Markers are set at 2 µm on the layout monitor to facilitate line placement.
Final feature sizes are determined by magnify and resize commands used in the CAD steps fol lowing layout completion. It is important to keep all precise capacitors and matched MOS device polygons on grid in the final mask dimensions. CAD snap-to-grid operations can severely degrade device balance and precise capacitor matching. The PLDR rule set, magnify and resize commands work together to eliminate the requirement for any snap-to-grid operations in the final mask-making steps.
A key feature of the design methodology is the ability to draw the original schematic using dimensionless notation. Our approach relies on the use of a single View Draw schematic and appropriate technology files to provide several required outputs: a schematic that guides the layout in PLDR using Cadence's (San Jose, CA) Analog Artist, a netlist in final silicon dimensions for simulation using View Analog, and a netlist in PLDR for initial layout verification (LVS) or a netlist in mask dimensions for final layout verification using Cadence's Dracula. Used in accordance with the techn ology files, Dracula's programming commands convert the PLDR layout data to final mask dimensions.
To make the schematic notation easy to read, the Pairgain methodology uses F in place of a decimal point on the schematic. For example, a gate length of 1F5 means a device drawn at 1.5F. A MOS device with the desired width of 4F and a length of 1F5 would have a W/L attribute of 4F/1F5 and be drawn at W=16 µm, L=6 µm.
Figure 2 - Testbench circuit
Simulating a dimensionless analog MOS circuit requires a testbench such as the one shown here. By creating a few alternative testbench schematics, you easily define certain worst case or nominal operating voltages, signal frequencies and load values simply by changing the pointer to the appropria te testbench file in the primary batch file that controls the simulation.
Additional notations define one of the few basic ways in which you can draw an analog MOS device. To reduce drain capacitance, for example, a single-drain diffusion might be shared between two devices of width 2F and length 1F5. The notation would then be 2F/1F5 SD M2, where SD and M2 designate a shared drain for a multiple of two devices.
The diffusions of analog MOS transistors are typically laid out in one of three basic shapes (see Figure 1): an unshared source (US) and unshared drain (UD), cascode drain (CD), and shared drain (SD). The UD configuration has the highest drain-diffusion capacitance. The CD diffusion can be shared with another transistor without requiring a contact and that configuration minimizes the common-source drain diffusion capacitance. The drain can still be SD if it requires a contact with either the same or another device.
In the simulation phase (see sidebar) following initial design, the goal is to improve the basic schematic without changing the test generators and power supplies. Once you finalize the circuit, you can vary the power supplies and temperature in simulation to verify the design. Capturing the test circuit and the testbench in separate schematics simplifies both simulation phases.
Because you use the same basic circuit schematic in all of the developmental testing and LVS work, simulation design verification and layout design verification always have the same point-of-reference. You can perform final simulation and LVS work on the circuit files after they have been placed in an archive directory under configuration control.It's possible to draw testbench schematics (see Figure 2) with different combinations of power supply voltages and loads. In the batch files that set up the simulation, you can then use INCLUDE statements to create the desired combination of test schematic and low- or high-power supply voltages and loads.
Preparing the netlist
A single schematic can generate netlists for simulation, layout verification in dimensionless notation, and final layout verification. The netlists generated for simulation and final layout verification use the same technology file. This file has magnify and resize values that result in device dimensions approximately the same as final silicon. The foundry often adds small resize values to a few layers to compensate for additional photolithography effects.
Another netlist is used for the initial PLDR-level LVS. No magnify or resize commands are used at the PLDR level. The feature size F is 4 µm and the resize is 1.0. Using the PLDR-level LVS technology file, a device with a 1F minimum gate length will have a final gate length of 4 µm. The PLDR-level LVS technology file is therefore always process independent.
The (see Table) table shows some typical technology file entries for scaling PLDR to fit a mixed-signal 0.35-µm process. The magnification factor of 0.125 redu ces the basic 4 µm drawn gate length to 0.5 µm. When you perform a resize of 0.075 µm on each edge of the digital gates (2 x resize value = 0.15), the final dimension is 0.5 - 0.15 = 0.35 µm. The analog gate edge resize is 0.025 µm. To keep precise analog device dimensions on grid, resize values must be compatible with the size of the reticle grid. Since a 0.125 µm reticle spot size is preferred at 0.35 µm for precise control of gate poly dimensions, the resize of 0.025 µm is on grid at 5x because 5 x 0.025 µm = 0.125 µm.
Note that the value of the unshared source/drain diffusion length is the same as the shared source/drain diffusion length between the gate poly. However, the drain area calculations split the shared length between two devices, thereby reducing the area by half. Once the basic technology files have been prepared, an in-house filter program converts the output netlist from the Viewlogic netlister's .CIR file to exact Spice parasitic values for each device. These values include AD, AS, PD , PS, RD, and RS for each device in the final .CKT netlist file used for simulation.
Once again, the simulator is your friend
The View Analog simulator was originally developed around BSIM models, which are enjoying increased usage as MOS devices scale down to shorter channel lengths. Current BSIM 3V3 models provide high accuracy in predicting short-channel output resistance-important in analog simulations.
The simulator includes a means of displaying algebraic combinations of instantaneous device node voltages and electrical parameters such as Vdsat in a multiplicity of real-time viewing windows. This combination allows for simple headroom (Vds - Vdsat) margin assessment over the full-circuit dynamic signal swing for all devices at all combinations of supply voltages, temperatures, and model speeds.
Although the View Analog simulator provides an extensive GUI, Pairgain designers use the simulator in the batch mode. The simulation TEST.SP control file contains the simulation real-time viewing parameters as well as operating temperature, timestep, and accuracy parameters. INCLUDE statements within the TEST.SP file combine the device model file FABT035NN.MOD; the circuit netlist SIM.CKT; and the testbench netlist BENCHNOM.CKT containing the signal generators, output load, and required bias and power voltage supplies (see Figure 2). An example script is thus:
INCLUDE FABT035NN.MOD INCLUDE SIM.CKT INCLUDE BENCHNOM.CKT
You only need to write this script once. Then you can use another batch file to invoke the netlister and simulator and point to any desired circuit name to test. For example, if the circuit is "TEST," the batch file points to the TEST.1 schematic file and the TEST.SP simulation control file. With that setup, you only need to modify the simulation scripts to point to other testbench netlists when you want to change conditions such as the combination of supply voltages. You can also set up different testbench and .SP control files for special purposes such as AC closed-loop, excess-phase measurements or device curve tracing.
You can size and arrange the multiple real-time display windows in View Analog to give a clear, though coarse, display of more than a dozen waveforms at once. This feature allows you to recognize events that might become obscured if combined in a few windows scaled in a manner similar to detailed waveform plots.
To obtain the headroom for an example PMOS bias device P2, you can give the headroom the alias VHRMPB2 and use the following script in the simulation control file TEST.SP:
The PRINT command is only required if you want to save the data for Vie w Analog's plotting tool.
You can see a magnified real-time display of the output/input voltage error in real-time using this script:
V(OUT) - V(IN)
While multiple real-time display windows provide a quick way to discover problems, View Analog's plotting tool allows you to focus on specific results. To see the simulation results in detail, for instance, you can display the waveforms from the first and second simulations in the plotting tool at high magnification.
Dropping to 0.18 µm and feeling good
The design example presented here describes the basic methodology developed at Pairgain for portable, scalable analog design. The true test of this methodology lies in the area savings possible in the final silicon, and Pairgain's success with the secon d-generation ADSL AFE chip layout has demonstrated the methodology's value. Other than design improvements and layer changes required to accommodate new capacitor technology, both analog and digital circuitry in this mixed-signal chip were automatically scaled from 0.35 to 0.18µm.
The automatic scaling saved approximately 1 year in design time that otherwise would have been required to re-layout amplifiers, comparators, switches, precise capacitors and logic components. If the analog portion of the chip had hadn't been scaled, it would have occupied 100 percent more die area and significantly increased the cost of the chip.
Lanny L. Lewyn is a principal Engineer in the Pairgain Technologies Inc., Microelectronics Group. He has over 20 years of experience in the design of linear ICs and currently resides in Laguna Beach, CA.
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