'Sea of blocks' speeds up SoC designs
By Jacob Greidinger, Chief Technology Officer, Aristo Technology Inc., Cupertino, Calif., EE Times
October 16, 2000 (3:44 p.m. EST)
All formal and informal projections show that leading-edge systems-on-chip will comprise 10 million, 20 million and even 100 million gates in a few short years. In the face of shrinking project timelines, designers will need a productivity rate of around 100,000 completed gates per hour within about four years to complete these massive designs on schedule. Yet, SoC physical designers find themselves equipped with design technology that supports 2,000 to 3,000 gates/hour at best, with little hope of dramatic improvement based on current methods.
Newer block-based approaches promise the next evolution of physical design by supporting blocks rather than cells as the basic physical design element. For SoC designers, this trend translates into design methods that view complex designs as a "sea of blocks" rather than the traditional "sea of cells."
Block-based design is the automated physical implementation of a chip using blocks as the fundam ental design element. For physical designers, a block-based approach means using tools that let them manipulate blocks comprising thousands of physical cells rather than individual cells as in traditional place-and-route methods. Just as hardware description language (HDL) abstraction methods have dramatically raised logic designers' productivity, block-based methods provide a higher level of abstraction that helps engineers quickly and reliably complete massive SoC designs.
Compared with the cell-based approaches that have been in use for the past 15 years, block-based design provides several advantages. One is scalability. Today's SoC designs are already exceeding the capacity limits of conventional flat physical design tools. By dividing up the physical implementation problem into subproblems that can be handled separately, block-based methods are scalable to handle designs of any size.
Block-based tools can produce partitions that are optimized for timing closure and design completion, be cause they can provide designers with early estimates of physical parameters at the beginning of designs, and increasingly accurate data as the design proceeds through block implementation. Armed with this data and timing-driven block-based automation tools, designers can eliminate costly design iterations and achieve design closure quickly and reliably.
Discrete blocks offer an easier route to reuse than working with IP that is mixed together into a large cell-based region. By using blocks where a specific function is implemented as a discrete physical unit, designers can implement their blocks to meet design specifications and validate them by taking the design block through the place-and-route stage. If they instead implemented their soft IP as part of a larger physical unit (such as a large flat design), they cannot know if their IP block meets design specs until a complete gate-level netlist is available for the entire physical unit to be placed and routed.
By handling a large design as a set of blocks, design teams can work in parallel on individual blocks, allowing them to design and validate their block without waiting for other designers to complete theirs. The inherent ability of block-based methods to support team-oriented development is particularly crucial and relevant as design organizations increasingly spread design projects across multinational design teams and adopt Internet-based collaborative design methods.
The ability to move easily between cell-based block implementation and block-level system implementation holds the key to dramatic productivity improvements offered by block-based design. Block-based methods complement rather than replace current cell-based methods. By partitioning designs into sections of manageable size for cell-based tools, block-based design approaches let design organizations continue to work with their existing cell-based tools and design flows. Furthermore, by providing information on full-chip performance th at's continually refined as blocks are implemented, block-based tools help designers focus their efforts on the optimum design strategies needed to achieve overall design closure.
The complementary nature of block-based design is evident in current ASIC design based on customer-owned tooling (COT) flows. Designers are already using COT ASIC flows to build 2-million-plus gate designs that exceed the capacity limitations of their existing cell-based physical design tools. As a result, these designers routinely partition their large cell-based designs into sections small enough to work through the cell-based tool set. This manual partitioning method, however, not only introduces initial delays required to create the partitions, but also leaves the design vulnerable to design closure problems. A design that is improperly partitioned from a timing point of view will not be fixable by the tools that later place and route the partitions. Designers need to use a partitioning methodology that is timing-driven .
New block-based tools such as Aristo's IC Wizard-COT can help improve the efficiency of these cell-based COT ASIC flows by automating manual steps-such as design partitioning and global routing-while allowing designers uninterrupted design flows through their existing tools. Besides providing timing-driven block placement and shaping, IC Wizard-COT offers automatic port placement, global routing and special signal-handling capabilities. In turn, designers can use their cell-based tools to work through the physical design of each section, relying on IC Wizard-COT to provide full-chip performance data that is continually refined at each stage of the design process.
IC Wizard-COT supports early estimation and incremental refinement by mapping chip-level constraints to block-level constraints, then passing these constraints to cell-based tools. As results become available, they are incrementally updated to the design database, displacing the earlier, less accurate estimates. At each stage in th e process, the tool recalculates global nets and port positions based on the data provided by the cell-based tool set. Through this continual refinement approach, the database augments the existing design flow with physical data that becomes more highly refined and accurate as the project advances. Finally, the ASIC designers are able to generate the final tapeout using their normal tools and flows.
The result is earlier visibility into design alternatives, earlier identification of potential problems and faster time to design closure.
In COT ASIC design flows, however, designers gain only a subset of block-based design advantages-specifically, scalability and design closure as described earlier. Many design organizations are gaining all the advantages of block-based methods by moving to "pure" block-based flows. Here, the design begins as a set of functional blocks and retains its explicit block flavor as individual blocks are refined through design and implementation.
In this approa ch, designers manipulate a set of blocks corresponding to hard IP, soft IP and even blocks whose implementation has not yet been identified-and rely on full block-based tools such as Aristo's IC Wizard-SOC to automate the block-level design functions. As with COT ASIC design flows, this fully block-based approach complements existing cell-based flows for individual block implementation. At the chip level, IC Wizard-SOC draws on its patent-pending analysis and layout capabilities to automatically perform block-oriented tasks, including block placement, shaping, optimization; interblock (global) interconnect routing, pad placement, pin assignment; and power and special net routing. In addition, this tool provides continually refined, electrically correct results through integral electrical analysis.
What's more, because block-based design provides physical design information from the earliest stages, designers who lack physical-design expertise are able to evaluate critical physical design characterist ics such as performance, area, aspect ratio, power, and clock schemes, voltage drop and electromigration. Tools such as IC Wizard-SOC provide physical planning of complex ICs early in design-well before register-transfer level (RTL) design-and generate increasingly refined results throughout the design process as more precise data come available from detailed design and analysis of individual blocks. In turn, designers can make key decisions very early in the design cycle-ensuring the design team's focus on the optimal design strategy from the beginning of the project. The result is an electrically correct design that is optimized for timing, area and power.
Block-based design offers the next great leap in design productivity because designers can work at a level of abstraction that lets them manipulate thousands of cells at a time. Just as RTL abstraction lifted logic design above gate details, block-based abstraction promises to raise physical design well above the limitations of current cell-based approaches and ensure faster, more reliable design closure.
Today's 2 million gate designs comprise only a handful of blocks. Yet, even with these designs, automated block-based methods are essential for completing physical design and achieving predictable design closure. Extrapolating even a couple of years forward, when leading-edge designs will comprise easily of hundreds of blocks, designers will find that the concept of a "sea of blocks" has turned into hard reality. In this environment, designers will find block-based tools and flows as the only reliable tack for completing designs quickly and reliably.