When Datum's engineering team set out to develop a new family of embedded synchronization solutions, it faced many challenges. This family of products, known as TimePieces, was designed to synchronize the transmission of voice, video, and data for a wide array of multiservice applications, including time-division multiplexed, Sonet, asynchronous transfer mode, code-division multiple access and Voice-over-Internet Protocol. The TimePieces chips had to be scalable and auto-configurable to handle constantly changing industry requirements. These chips were designed to work around a core chip known as SmarTiming, which would measure, qualify, and select input references based on system requirements and then output a very stable, accurate and reliable timing signal.
Designed to be used stand-alone or as a timing system, the TimePieces chips communicate through a patent-pending protocol referred to as the TIB (TimePieces Interface Bus). Through t he TIB, TimePieces automatically configure interconnected chips into timing systems. This allows the end customer the freedom to utilize individual chips to meet a specific need, or build whole systems to meet their sync needs for each application.
Each chip is designed to meet specific portions of the various telecommunications timing standards. When operating as a system, it is possible for the end customer to meet whole timing system specifications. The basic functionality provided by a chip set system includes custom I/Os, Stratum 3 or 3E oscillator, a standard-based timing controller and an 8-bit parallel library communications.
In order to provide the needed functionality and design flexibility, each solution required a minimum of a microcontroller and some type of configurable logic. Because of certain application constraints, Datum chose the standard footprint size for the board to be a 68-pin and an 84-pin PLCC measuring just over an inch square. Datum also needed to develop the Ti mePieces family quickly in order to meet critical customer demands.
Datum explored the use of a microcontroller and an FPGA but was faced with design issues. A standalone microprocessor was very limited by the RAM and flash storage available on-chip, and with the addition of an FPGA, the design violated the board size constraints laid out in the selection of the standard footprints.
With just over a square inch of board real estate in the largest footprint, the designers were faced with the task of getting as much functionality as possible into the small footprint. With TimePieces aimed at the OEM market, the designs were also cost-sensitive, and most solutions exceeded the cost budget laid out by the marketing team.
By integrating Triscend's E5 Configurable System on Chip (CSoC), Datum was able to get more usable gates than with a microcontroller/FPGA combination, and the design still fit within the small footprint dictated by the PLCC. Triscend's CSoC solution also provided the bes t time-to-market scenario.
Basically, the Triscend E5 CSoC integrates, on a single device, a performance-enhanced 8032 "Turbo" embedded microcontroller, embedded programmable logic, a high-speed dedicated system bus, and a large block of SRAM intimately connected to the processor and system bus. The E5 provides a highly integrated, fully static single-chip platform that can be quickly optimized for a wide range of embedded systems applications.
The embedded high-performance 8032-based "Turbo" microcontroller is instruction-compatible with other industry standard 8032/52-based devices. Thus, Datum was able to leverage the vast software library for the 8032 architecture.
The embedded SRAM-based Configurable System Logic (CSL) matrix provides "derivative on demand" system customization-up to 40,000 gates. The high-performance configurable logic architecture consists of a highly interconnected matrix of CSL cells. This embedded configurable logic allowed Datum to rapidly evolve product designs to match changing industry protocols. Resources within the matrix provide easy, seamless access to and from the internal system bus.
A large block of fast, byte-wide SRAM provides internal storage for temporary data or for code. Though typically used for data, code can be executed from internal RAM, offering faster access plus security in battery-backed applications.
The E5's IEEE 1149.1 JTAG port offers nearly full access to the microcontroller, peripherals, and CSL functions to aid in debugging. The JTAG interface can become a bus master on the internal CSI bus. During system debugging, the JTAG port also sets up the internal hardware breakpoint unit.
The debug time in a design cycle is usually the most arduous and time-consuming phase of design. Because of the in-circuit testing and development environment provided by Triscend's FastChip development software, Datum was able to spend less time in debugging the design, thereby reducing time-to-market. Utilizing this envir onment, Datum was able to perform all debugging and development for both hardware and software through a single JTAG port. This was particularly attractive because there is a blur of hardware/software functionality within the TimePieces devices. The ability to have the hardware and software developers utilizing the same development environment aided in shortening the project time.