Real Pomerleau (Cisco), Stephen Scearce (Cisco), and Tom Whipple (Cadence)
1/16/2011 11:47 PM EST
Since the dawn of semiconductors, the dies, the packages, and the boards they reside on have typically been designed by different teams that focus their expertise between predefined boundaries.
Most have seen those flows where the die design gets thrown over the wall to the package designer, who then designs the package and throws the package footprint over the wall for the Printed Circuit Board (PCB) designer to incorporate into the board design.
As design speeds crept through the low hundreds of megahertz range, Signal Integrity (SI) engineers started to worry about signal power integrity (PI). Design teams started to realize that simply connecting the dots is a bad interconnect strategy, and the sprinkle-and-pray approach to decoupling capacitors became an expensive and risky approach to power integrity.
As clock speeds reached up into the mid-and upper-hundreds of megahertz range, second order effects that could be ignored before began causing significant problems. For example, package skew had to be properly accounted for in the overall interface timing. Package decoupling that used to help mitigate power integrity issues was no longer effective. These problems quickly became evident even though due diligence for SI and PI was done at the PCB level.
Today, memory interfaces have single-ended data rates in the 1GHz-plus range, and serial links are running upwards of 10 gigabits per second. The “throw-it-over-the-wall approach” has become completely ineffective. A precise design, analysis, and rules-based control of each of these signals is required at the die, package, and PCB level. The analysis and optimization performed on each one of these interconnection levels must be done in a global context.
The problem presents itself in both the electrical and physical domain. When designs are “thrown over the wall”, they are typically done by someone with little knowledge of the overall constraints of the system.
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