James Young and Michael Sanders, AMD Inc., Paul Graykowski and Vernon Lee, Synopsys Inc.
EETimes (1/19/2011 9:19 AM EST)
In order to deliver ever increasing performance at bounded clock frequencies, processor vendors have turned to multicore designs that allow many programs to execute in parallel on a single chip. Verification of a multicore design is substantially more complex than a single core design because access to shared resources, such as the memory and I/O subsystems, requires arbitration and coherency. Not only general purpose processors, but embedded and application-specific processors such as graphics processing units (GPU), must be verified using large regression suites.AMD continually pushes the technology envelope to develop highly complex multicore processor chips. Verification of such multicore processors involves the execution of tens of thousands of tests in a typical regression. As this regression can take a week or more to execute, there is a need for designers to have available a highly optimized test list that maximizes line and toggle coverage. It is important that this test list can be run and graded in a matter of hours. The optimized list must be bounded by a predefined number of tests, such that the run time of the resultant mini-regression can be modified to meet scheduling needs.
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