Kirk Jensen, Lattice Semiconductor
EETimes (1/23/2011 4:15 PM EST)
Clock signals in synchronous digital systems (such as those found in telecommunications) define when and how quickly data is moved through that system. A clock distribution network, consisting of multiple clock signals, distributes those signals from a shared point to all of the components in the system requiring clocked data. Because the clock signals perform a critical system function, it is clear that more attention should be given not only to the clock’s characteristics (i.e. Skew and Jitter), but also to the components that comprise the clock distribution network.
FPGA development teams are consistently challenged by overly burdensome, complex clock networks. Various factors, including increasing demand for I/O, cost reduction opportunities and the need to reduce PCB design changes, are forcing another look at those clock networks. This article examines FPGA clock distribution control challenges that are motivating development teams to change the way they design, and offers practical advice for designers who are considering ways to enable additional FPGA I/O, or improve clock network performance, by reducing the size of their clock distribution network.
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