Despite a push to automate and mechanize design reuse, large complex designs still evolve, almost organically, from the digital soup of those that came before. While some useful IP standards are emerging and EDA vendors are making a lot of noise about the reuse capabilities of nearly every tool, the fact remains that design reuse and IP integration are by and large ad-hoc opportunities, not highly refined processes.
Most design elements that are reused today have not been designed specifically for the purpose. These elements are mostly parts and pieces of older designs adopted by the current design team for reasons of expediency. Sometimes they are commercial offerings that must be customized to the task at hand. Often the make/reuse/buy decision is a close call because incorporating an existing design element might be nearly as difficult as designing from scratch.
System-on-chip (SoC) designs comprise logic that spans new code, reu sed components and intellectual property purchased from others. Debugging such designs requires understanding all the parts and how they work together. A debugging system helps engineers understand complex and unfamiliar logic by letting them rapidly trace and visualize the cause-and-effect relationships so they can more easily locate and isolate the reasons for bugs.
To reuse a design, the engineers must understand it. Even designs that are specifically sold for reuse are not documented adequately. Most times, designers are forced to reverse-engineer the operation of the part they want to reuse. Further, when designers incorporate the part with the other elements of their design, they must verify that the resulting combination behaves as expected.
Verification of complex behavior is difficult enough when the engineers are familiar with all of the logic. Reuse and IP compound the problem by turning some of the boxes black. Black-box verification is extremely difficult, if not impossible. When ever unexpected behavior is spotted, the symptom must be traced through the design to its source. When that behavior spans more than one block in a design, debugging becomes more difficult. When the behavior involves blocks not designed by the engineer doing the debug, the difficulty, time and cost of debugging increase rapidly.
Determining the cause of erroneous behavior is a grueling process that involves examining many parts of the design, comprehending how they contribute to the observed behavior, eliminating those that are operating correctly, isolating those that are not and understanding why. Several levels of hierarchy, dozens of files, hundreds of signals and thousands of lines of code may be involved. Cutting through the maze is essential to rapid debug of functional problems in large complex designs.
Contributing to the difficulty of debugging is the fact that verifying today's designs requires many different tools. Each tool employs its own representation of the design for analysi s. But when users try to understand the results of the analysis and debug the problem, they confront inconsistent design viewers and commands.
A debugging system such as Debussy from Novas Software Inc. can help designers combat those complications and contain debug costs. The architecture of such a system makes it a universal platform for debugging the results from many verification and analysis tools. Its features, which include tracing, visualization and automatic debugging, provide the means to understand designs and quickly locate and isolate the part of the design responsible for unexpected behavior. That makes a debugging system an essential element in the design flow that involves design reuse and IP.
Understanding an unfamiliar design starts with tracing the connectivity and structure of a design through its hierarchy and its source code. Engineers need easy ways to traverse the hierarchy and immediately see the source for any part of the design, then trace drivers and loads by means of simple point-and-click and drag-and-drop operations. Through visualization of the design and annotation of simulation results directly on the source view and in the graphical representations, engineers move another step toward thorough comprehension of design behavior.
Annotation makes it easier to understand how each line of the code, bus and signal is contributing to the design's behavior. Linking these to the waveform viewer and to an efficient database that stores signal value changes over the course of simulation time is essential to provide rapid traversal of the results in the context of the design.
Having a single view of the design across multiple verification tools is important to maximize debug efficiency. To accomplish that, a debugging system compiles the original source files, giving users a clear view of the design that is not affected by the processing of any particular verification tool.
Vweb Corp. (San Jose, Calif.) develops complex system-on-chip devices to enab le digital video on the Web. Those designs, which implement digital video compression and distribution technologies, both incorporate IP and will themselves be reused by system designers. Vweb's MPEG encoder design demonstrates the difficulty engineers face today. The design combines outside IP for interfaces such as PCI, Firewire and two RISC processors with a high-performance custom engine consisting of 22 separate state machines and more than 20 memories.
Use of the Debussy debugging system accelerated Vweb's design and verification process by making it easier for designers to understand code written by other engineers. It seems clear that IP integration and design reuse save design time, but they also increase the debug burden because they add lots of unfamiliar logic to a design. Users often find that they must effectively reverse-engineer that code in order to optimize their designs and verify that the reused components work correctly in context.
Use of a debugging system has been shown to cut debug time and costs by a significant margin, particularly in large complex designs where the engineers are debugging other people's code. Many users estimate savings of 30 percent to 50 percent.
Those savings are particularly important because debugging is an interactive process that carries enormous opportunity costs.
Because engineers cannot add new chip value while they are debugging old problems, it is essential that design and verification engineers have better ways to understand complex and unfamiliar designs.