Building an infrastructure for IP reuse
By J. Scott Runner, Director, Platform Technologies Division, Venu Sanaka, IP Solutions Engineer, Elaine Yu, IP Repository Release Manager, Conexant Systems Inc., Newport Beach, Calif., EE Times
May 15, 2000 (2:22 p.m. EST)
Designs have been reused ever since they have existed. However, the motivations for investing in effective ways to reuse intellectual property (IP) have changed significantly and will continue to do so.
Historically, reuse efforts were aimed at efficiency and quality, enabling engineers to develop more new things that worked. This goal could be achieved to a large extent through ad hoc techniques such as consistent directory structures, common libraries and configuration management at the project team level.
However, IP reuse objectives are now becoming more aligned with overall business strategies. The driving force is technology convergence. On one hand, convergence delivers a greater variety of more integrated products with richer features at a lower cost-and does it faster. But on the other hand, such levels of integration require technologies and competencies beyond the scope of most companies. And even if they have those techn ologies and competencies, they often cannot integrate them because of differences in design methodologies or an inability to coordinate disparate design teams.
Design reuse has a life cycle. It begins with the creation of IP, moves on to packaging it for reuse and then to the integration and subsequent reuse of a design. Since reuse is not an end in itself but a means of enabling overall business objectives, IP reuse differs from IP leverage. The latter is the process of utilizing IP to generate revenue, broker important partnerships and develop an innovation engine to create highly integrated cross-disciplinary system-on-chip (SoC) devices that outpace the competition's cycle time.
Thus, the value of reuse is really the value of leverage, and a true return on an investment model for reuse should consider the leveraged benefit, not simply the time savings. For example, a 100 percent cost to desig n a function for reuse may yield a savings of 50 percent when it is subsequently integrated, which implies a break-even point of two reuses. Ten reuses may save four times the original development cost (500 percent minus 100 percent equals 400 percent). For a complex function requiring two person-years of development cost, this may translate into eight person-years or nearly $1 million in cost. Alternatively, one could have applied this same effort to IP that would have been reused three times, saving only $100,000 but creating an opportunity that generates $100 million in revenue.
At Conexant Systems we have a rich array of communications technologies from which to quickly create a variety of complex high-quality products. And while importing key external IP is critical to our success, we have extensive IP that is internally leveraged to make a significant market impact. It is thus our focus to create a highly effective environment for reusing and leveraging IP enterprisewi de or corporatewide or both, for the greatest benefit.
We use a five-level capability model for IP reuse to achieve this road map. The first level, ad hoc reuse, refers to the process of reusing IP without an explicit corporatewide IP reuse program. Thus, the organization benefits indirectly from advantages realized by the particular design team. But when IP designed by one team employing ad hoc reuse is integrated with that from another design team or external IP provider, many problems typically surface.
Often SoC design teams integrating such components compromise their designs, since models are not available to support efficient SoC design flows. Clearly, ad hoc reuse will not work for today's SoC designs, and any company struggling with those matters should revamp its SoC and component-creation methodologies quickly.
The second level includes IP awareness. This can be the "low-hanging fruit" in implementing an IP reuse program. Providing awareness, or visibility, of what IP is a vailable in the company and in the industry can enable SoC designers to design systems based on available components, create visibility into what has been designed to avoid duplication of efforts, promote leverage among multiple applications and foster coordination of requirements for multiple target applications.
At the third level is design for reuse. Much has been said and written about DFR and much debate has ensued about what is a reasonable investment for effective DFR. Many of us can relate to the effort required to reverse engineer, or mine legacy IP to make it reusable.
Examples often cited are full-custom microprocessors and digital signal processors that must be migrated to new processes and exported to IP integrators that are not generally thrilled about their experiences. Repackaging IP can consume up to 200 percent of the original design effort.
However, when IP is designed for reuse leveraging higher levels and the like, it can typically be reused im mediately, or at least more quickly than components that must await mining. However, the DFR effort may require 50 percent to 100 percent overhead; something that overwhelms designers as their designs grow in complexity with shrinking design cycles. However, you can pay now or pay later, so try to ensure that you have at least a minimum set of DFR guidelines that all designers follow and that provides for a high return on your DFR investment.
At the fourth level is collaborative design. Many companies have found that their work has only begun once the IP has been packaged. The following scenario is common: The IP team packages selected IP, generating all necessary views and verifying them. However, it may still not be highly relevant in terms of how well it functionally satisfies the target. Increasingly, the time span between the initial use and the first reuse is shortening to the point of soon becoming concurrent.
Collaboration among semiconductor end-system vend ors, as well as IP providers and others, is becoming increasingly more common in SoC designs. Such real-time collaboration demands a dynamic reuse model as opposed to the traditional static one.
This emphasizes that views of IP must be generated, verified and shared as the initial design proceeds, not after it is packaged.
Furthermore, IP has a way of morphing with each subsequent reuse.
The best way to leverage the changes that are made to the IP is to create a model akin to the open source model made famous by the Open Software Foundation.
Here, users are free to implement bug fixes and enhancements to IP, provided that they check those changes back into the repository. Packaging IP and self-certifying the resubmitted IP permits the derivative IP to be readily reused. This "closed-loop" feedback system helps ensure a content-rich, content-fresh IP repository.
At the fifth and highest level is business-to-business IP collaboration, currently a hot topic of discussio n. While the infrastructure for Web-based e-commerce of IP is being defined and implemented, it is not critical yet to the operations of many semiconductor companies with large repositories of internal IP. However, in the near future the ability to leverage IP assets to customers and partners will make the transition from being an advantage to a necessity.
The concerns to be worked out in this area demand the formation of industry standards to address views and data organization, security, interconnect, etc.
The concerns are being addressed by industry associations such as the Virtual Socket Interface alliance (VSIA) and VCX. If industry standards will be required for that level of IP interchange, then it is obvious that any guidelines for IP creation and packaging should be aligned with the industry standards that are becoming pervasive.
Of current industry standard work, there are activities with midterm and long-term benefits. IP interconnect standards, manufacturing test and st andardized views and data organization, and standard business models and IP licensing contracts can not only have an immediate effect, but can also lay the groundwork for the future.
Security and standardization on system-level languages are essential to future IP representation and protection.
The culmination of those industry activities, with active participation from a variety of electronics companies, should enable an industrywide IP ecosystem to emerge and flourish.
In this environment, IP creators and integrators become enmeshed in a web in which security, licensing and collaboration are becoming more burdensome. Solving those problems will enable the industry to leverage IP at an accelerated pace. It can allow IP to be exchanged among creator, integrator and semiconductor vendors as easily as IP can be downloaded to an end customer's platform.
Increasing the capability for collaboration to link the entire IP life cycle will become more impor tant as SoC design roles blur and become more distributed. Extranet IP supply-chain management systems are required to effectively accomplish that type of collaboration.
Tighter integration with external IP distribution will marry with tighter SoC collaboration and systems for capturing and reusing knowledge. Collaboration will move to true real-time collaboration with low latency in exchanging views of IP components being essential.
Knowledge management may turn out to be the greatest form of IP to leverage. In this emerging information age, it will become very significant for designers to share know-how, decisions and information characterizing design.
A key goal is to work closely with the IT organization to make that opportunity a reality. In the end, IP leverage, not just reuse, will be the engine for the creation of products that truly enable technology convergence.