Despite the apparent productivity benefits of reusing preexisting design material, the unfortunate reality is that even engineers who reuse internally developed logic struggle daily with tough problems. Hidden in any reuse project are unknowns that stem from such factors as differing original and reuse design teams, evolving design methodologies, and process technology differences.
Discovering and fixing such hidden "gotchas" before they jeopardize precious time-to-market objectives can mean the difference between product success and failure.
We in the ASIC Design Center of Siemens' Information and Communications Networks (ICN) group have devised a design methodology that addresses the challenges unique to reusing preexisting logic. Our methodology relies heavily upon static timing analysis (STA) and advanced diagnostic design tools to enable the successful reuse and verification of legacy intellectual property, even when not origin ally designed with reuse in mind.
Last year, we successfully applied this methodology to the respin of a complex telecommunications function. Without the benefit of access to the original designers, we achieved first-run success on a respun product with 55 asynchronous clocks and other design complexities. The challenges we encountered in this project are similar to those faced by any designer attempting to leverage preexisting design content in new, more advanced applications. Our methodology, as demonstrated in this design respin example, stands to benefit any designer hoping to revamp vintage design content.
Several unfortunate realities impose tough problems for anyone designing circuits in the telecommunications systems mar-ket. The fast pace and highly competitive nature of this marketplace dictate the development of increasingly complex products within increasingly narrow market windows. At the same time, the 15- to 20-year longevity of hardware for telecommunications systems requires that higher data rates, greater bandwidth and evolving standards be accommodated with backward compatibility for substantial preexisting investments.
Intellectual property reuse, because of its promise of high productivity design cycles and inherent backward compatibility, is therefore a cornerstone of our design methodology. Indeed, within ICN's Transmissions Systems Division, our evolution to a platform (or reuse) design approach is evidenced by the content of our projects-typically 50 percent to 95 percent preexisting, internally developed content.
Despite the apparent simplicity and intuitive appeal of reuse for our purposes, imposing challenges face us in these design projects. The majority of functions to be reused are seldom originally designed for reuse, meaning that documentation is often lacking or nonexistent and that design HDL coding may also be poorly suited for deployment in today's design environments. In some cases, the original coding may hav e been for a pc-board implementation and is not ideally suited for silicon-based deployment. Design methods for synthesis and other aspects of the design flow evolve over time, presenting syntactical and other technicalities that must be worked through.
To complicate matters, the original designers are typically unavailable to provide essential insights into critical design questions.
The respin of a key ASIC in a transmission system presented those challenges as well as others specific to the composition of the circuit. In this version, the third in the 150k-gate (with 100k bits of on-board RAM) ASIC's six-year lifetime, we set out to meet a customer's need for support of a new telecommunications standard as well as to upgrade the chip to higher-performance, 0.35-micron technology. The design was originally handcrafted to optimize its performance, making direct synthesis into a new technology problematic and risky. Additionally, 55 asynchronous clock domains within the circuit itself posed a tremendous verification challenge.
Further, we did not have access to the original designers, so we were working with limited knowledge of the circuit and its critical timing paths. Finally, the move into deep- submicron technology required that we comprehend on-chip performance variation in our flow for the first time. Indeed, our silicon manufacturer even requires that cross-chip delay tolerance be calculated as a condition of sign-off. With increasing design complexity, accurate modeling of on-chip process, voltage and temperature variation is becoming more and more important.
It became clear early on that our verification strategy for the project was critical. The process technology change and additional functionality for the new standard would have a definite impact on the timing of this already highly optimized and sophisticated system. The biggest challenge was uncovering the design's existing unknowns and newly created unknowns resulting from the changes to the design. Our limited kn owledge of the system demanded that our functional and timing verification methods be exhaustive, comprehend full-chip functionality and offer intelligent diagnostic capabilities.
A traditional simulation-based approach highlights only that something is wrong without identifying whether it is functional or timing-related or where it is located. That would not suffice for this project.
At the same time, market pressures dictated that verification and analysis techniques be highly productive.
We determined that static timing analysis and formal verification would be the optimal means to validate timing and functionality, respectively. The 100 percent coverage provided by each of these techniques is particularly critical in redesign projects in which the design team has limited knowledge of the original design content. Full chip verification is particularly critical in the highly complex chips being developed today. For example, the conventional approach to STA at the block level within a synthesis environment simply can't catch all errors. To eliminate the possibility of missing errors in the fully assembled chip, interblock interactions and full-chip functionality must be comprehended.
Selecting the appropriate STA tool was of particular importance to us because the static timing tools we had used previously could not resolve the complex clocking issues native to this circuit. After a thorough exploratory process that entailed the examination of approximately 100 different factors, we adopted the SST- Velocity STA tool from Mentor Graphics Corp. (Wilsonville, Ore.) in our design flow.
This tool not only addressed our critical needs for both on-chip variation analysis and automatic analysis of complex clocking schemes such as asynchronous and gated clocks, but it also offered other advantages specific to design reuse. The tool is easy to use, intuitive and fast. Its incremental analysis capabilities enable it to deliver answers interactively and rapidly, regardless of desig n size. These critical attributes-on-chip variation analysis, the ability to handle complex clocking schemes, ease-of-use and productivity-made SST Velocity an integral part of our reuse flow.
Our design flow for reusing logic is straightforward. Starting typically with the hardware description language (HDL), we perform synthesis for technology mapping and chip assembly. We then perform full-chip static timing analysis and formal verification. At each point in which the netlist undergoes modification such as gate resizing, clock tree and test insertion, we perform formal verification to ensure that functional integrity has been retained. We may also perform block-based simulation on specific elements, as needed.
"Design discovery" via STA completes the initial logic design flow. With STA we identify such design attributes as false and multicycle paths, underlying clock structures and missing constraints. With the special capabilities of the SST Velocity tool, automatic links between reports and schematics allow us to immediately pinpoint the exact location of problems, critical clock locations and clock domain boundaries.
We follow with three layout stages. In the first stage, we perform a trial layout of the initial design to highlight any major placement and routing issues. Once any errors are fixed, we then resize the buffers as needed, using our STA tool to reanalyze changes incrementally and interactively. We use the same tool to perform "what if" analysis and take advantage of any timing margins that might improve performance. We perform STA, formal verification and limited simulation on the resulting layout, make any needed corrections, and proceed to final layout.
Applying our flow to the transmission-system ASIC posed some unique challenges. To get a quick and reliable view of how the circuits were originally designed, we performed initial design discovery using the SST Velocity tool. In this phase we were able to ascertain basic compositional information such as the st ructure of clock trees, the number of gated clocks and the number of asynchronous clock domain crossings. We knew that constraining a design with more than 55 asynchronous clocks would be a tough job, so we used the SST Velocity tool to identify asynchronous clock boundaries. In a single analysis run, we were able to examine a clock domain crossing report that detailed both synchronous and asynchronous domains and identified both source and destination flip-flops.
During our design discovery process with the static timing tool, we uncovered several hidden problems that we quickly fixed. An automatically generated gated clock report highlighted two errors that, upon further exploration with the linked schematic windows, we learned were related to a problem in the translation between 0.5micro and 0.35micro technologies. We promptly fixed the problem and averted first-silicon failure.
The SST Velocity tool also detected design errors resulting from a difference in how synthesis was run in previo us spins of the design. The errors were highlighted in an automatically generated report, and we used the schematic viewer to examine the problem in context. We found that the problem was not isolated to one block, and we traced the signal between blocks to find the problem areas. We repaired a pulse generation circuit as well as a gated clock as a result of this discovery.
Reuse is, and will remain, a vital aspect of successful design strategies. In the process of developing and applying this flow to many successful complex ICs, some ranging over a million gates, we have realized the value of highly productive analysis and diagnostic tools such as SST Velocity. With such capabilities, we've found that we can confidently identify and fix reuse-related problems more rapidly and with much better insight than with alternative approaches. There is no doubt that we will continue to adapt our flow as new challenges present themselves, and advanced static timing analysis capabilities will remain a critical component in our design reuse methodology.