SoCs: Design tools -> Raising the reuse bar with processors

Complex intellectual property (IP) intended for reuse cannot be a simple static circuit block. Rather, it needs to be generated from a systematic framework of tools and methodologies that fits into both the design environment and the target application for which the intellectual property is intended.

Several requirements such as a good feature set and compliance to industry standards ap-ply to any design intended for reuse. In addition, complex intellectual property requires ease-of-use, design environment independence, customization and c ompleteness.

Since a major reason for reusing a design is to enhance designer productivity, it must be easy to use. The amount of detail in the design of a complex intellectual property like a processor can easily overwhelm any system-on-chip (SoC) design team. The challenge for the intellectual-property developer is to abstract the details not relevant to the system design and give designers easy access to those that are needed to implement and integrate the intellectual property.

Tensilica, for example, addressed the need to parameterize the various interfaces to the core with a unique Web-based processor configuration tool. The Xtensa Processor Generator enables rapid creation of optimized application-specific 32-bit processor cores. The interface allows designers to specify the desired attributes without worrying about either the processor's internal details or the correctness of each choice of parameter. The Processor Generator will only allow building of "legal configuration." As each c onfiguration option is selected, its estimated impact on area, timing and power is provided to the designer.

A design intended for reuse cannot be tied to one design environment. Since moving a complex intellectual property from one environment to another can require significant resources and impact its quality, it's best to develop the intellectual property to be independent of the design environment from the start.

During Xtensa's development, we adopted a strict design methodology to ensure that the design was truly reusable. Although a full custom design gives better area and performance, we chose a fully synthesizable implementation since it enables quick portability across standard-cell libraries. We used a restricted coding style to enable Verilog sources to be easily translated to VHDL, prohibited use of design structures such as tri-state buses, and restricted the use of latches to only well- controlled areas of the design such as register files. Another design objective was to have the design operate with widely used simulation and synthesis CAD tools. To enable this we avoided using tool-specific pragmas and directives.

Each SoC design will typically have unique requirements driven by its target application. This requires that the system designer be able to customize a reusable design. A hard block that cannot be altered will result in a suboptimal solution since the system and the application will need to be designed around the fixed hard block. Consider an example of two SoC projects-one requires a 128-bit system interface for optimal application performance and the other requires only a 32-bit interface. Except for this difference, the desired underlying processor functionality is identical. Taking the core with a 128-bit interface and altering it manually to create a 32-bit interface, while certainly possible, is undesirable since it is error-prone and creates a significant verification problem.

A different kind of user customization is where the designer wants to extend the reusable intellectual property by adding his/her own IP. Let's say a designer's application spends significant time performing the Huffman decode function. Most processors do not have an instruction for this function. If the SoC designer can extend the processor instruction set with an instruction for Huffman decode, the application's performance will be improved. The ability to add application-specific instructions is a powerful tool for boosting application performance. Again, a designer can edit the original processor RTL for instruction additions, but as discussed earlier, this is not desirable.

The Tensilica Instruction Extensions (TIE) language lets designers add instructions to the processor implementation, complete with full software support for generated instructions. Designers have used TIE to increase the performance of 32-bit processors by five to 50 times in applications such as image compression, packet forwarding and data encryption.

A complex reusable design must pr ovide a complete solution for it to be most effective. For a processor core, having reusable RTL alone is not enough. The supporting software tools also need to be reusable. Any end-user hardware customization must also be reflected seamlessly in the software tool-chain for effective reuse. Since the SoC designer will not have detailed knowledge of the implementation details of a complex intellectual property, the IP deliverables should cover all aspects of the design implementation and manufacturing process.

The Xtensa processor generator generates all software tools and hardware descriptions for the final application-specific processor. This includes complete documentation, the RTL, an HDL testbench, vectors for functional verification and production testing, simulation scripts for RTL and gate-level simulations, synthesis scripts, physical implementation files, C-level simulation models and an emulation kit.

The higher the complexity of an intellectual property, the higher the expected qua lity. This is because the SoC rework cost of reintegrating a complex intellectual property can be substantial. All aspects of the product need to be thoroughly verified.

Tensilica has developed an elaborate verification environment to verify the Xtensa processor RTL that can be easily imported into the final SoC testbench. The verification environment includes directed and random diagnostics, lock-step checking of RTL with respect to an instruction-set simulator, cache and bus interface protocol checkers, etc. Hundreds of millions of regression tests have been run and continue to be done to ensure quality. The Xtensa core has also been verified using software applications and operating systems on an emulation board.