SoCs: Design tools -> Hard IP offers some hard-core values

Reusing existing hard IP is becoming a fact of life for design teams because demand for more complex designs is having an effect on project schedules. Product life cycles are becoming shorter, demanding shorter design cycles for each new product generation.

The hard IP reuse methodology enables designers to efficiently implement SoCs and permits them to optimize that IP for performance or power. The same methodology can also be used for new designs. With deep-submicron designs, timing closure is becoming a bottleneck. Hard IP optimization, therefore, is an important consideration for both reuse and design.

Semiconductor processes are also facing a shorter life span with each new generation-as short as 18 months for 0.18-m processes. Deep-submicron processes are making the final mask design stage more critical and time consuming, due to increased parasitic effects that influence timing and functionality. This forces design teams to implement some form of process independence into their design flow.

By definition, hard IP reuse involves taking a mask-level designed block, in GDSII format, and modifying it for a different process. Since this method involves a polygon-level relayout, it imposes inherent demands on the similarity between the processes concerned-migration from a GaAs to a CMOS process is generally not possible, for example.

There are several advantages to hard IP reuse:

- A hard IP block has already been proven and verified in silicon, making its reuse more reliable.

- IP in hard form is better protected from illegal reuse.

- Reuse of hard IP allows the original software to be reused without modification.

- Hard IP reused with circuit optimization and automatic layout makes it possible to optimize performance and power consumption simultaneously.

Various methods exist for designers to reuse hard IP. Optical shrink, polygon-level relayout, and layout migration are the most well-known.

The optical shrink technique is successful and reliable. Despite the inherent area penalty, a shrink can be reasonably efficient, provided that process design rules were optimized to allow for a good shrink-path. With deep-submicron processes, however, shrinking is hardly an alternative. A nonlinear relayout of the design is the required approach.

Polygon-level relayout, traditionally known as polygon compactors, produces a design r ule correct version of a block from raw GDSII and a design-rule description. For a proper fit into a real-world design environment, more is needed than just fitting polygons onto minimum design-rule coordinates. This is achieved by layout migration, of which polygon compaction is only a part. Layout migration controls transistor sizes, power supplies, via-doubling and contact optimization.

Layout migration software is the optimal solution for hard IP reuse because it guarantees optimal design density by positioning each polygon edge individually to optimum locations and enforcing the physical design rules. Since layout migration also involves exact control over each individual device size, it is also a perfect tool for manipulating transistor dimensions in the final layout to tune the design for performance and power consumption. Designs can be migrated and optimized using layout migration in combination with circuit optimization.

Hard IP optimization can also be a goal in itself, separate fr om migration. For full-custom designs in an ultra-deep-submicron process, trying to estimate interconnect capacitances and the necessary device dimensions from a schematic design has become unfeasible for larger blocks. The final interconnect capacitances depend largely on the physical implementation, requiring device sizes to be modified even after layout has been drawn according to the specification.

As a result, many IP blocks are not optimized for performance, area, power consumption and yield. A hard IP optimization flow can improve speed and power characteristics. Objectives for optimization can be any combination of performance, power consumption, silicon area and manufacturability, depending on design specs and production volumes.

The optimization can serve as a final step in the design of new IP, by fine-tuning each transistor for exact load. This fine tuning is also applicable in a reuse context, where new transistor dimensions may be chosen to make a migrated design fit requirement s of the new manufacturing process.

The optimization source is always some form of hard IP, regardless of the way it was created-full-custom design, place and route or migration, for example. Since the objective is to tune each transistor to its exact loading, a resistance/capacitance (RC)-extraction from the original hard IP is performed, which yields a Spice file. The Spice representation serves as input to a circuit optimization program that will determine new transistor width and length parameters, ensuring requirements are met. The circuit optimization is the part where most of the user interaction takes place. In several optimization runs, a balanced trade-off is found between required performance, power consumption and silicon area.

The compaction engine-or the layout migration software-is given the task to implement each of these new transistor sizes on the original design.

For most transistors, this means they will be reduced in size, because a worst-case drive capability wil l have been used in the design. Some transistors will need to be enlarged-such as devices on the critical path for delay time.

As an example, the optimization flow described below was used to design a 16-bit multiplier, implemented by a 10,005-transistor datapath-style, full-custom design in a CMOS 0.25-m process.

Electronic design automation software used included Amps and Arcadia developed by Synopsys Inc. (Mountain View, Calif.) and the Hurricane compaction software from Sagantec.

Delay time was selected as the primary target. Bottom-line results showed that delay could be improved by 11.7 percent at an area increase of only 2.6 percent. The target performance enhancement for Amps was defined to be a 10 percent gain compared to the original design. Results from Amps predicted a slightly better performance. All device sizes as specified by Amps were implemented correctly by Hurricane, leading to an optimized layout 2.6 percent larger than the original.

A second Amps run was performed, now limiting the maximum growth of a transistor width to 4 microns for an NMOS gate and 5 microns for a PMOS gate. Amps was now forced to increase more transistors in size, but only moderately.

This illustrates the advantages of using a hard IP optimization flow. An improvement in speed was obtained without logic redesign and with only a minor increase in silicon area. The original design was leaving performance on the table, even though it was designed as a full-custom block to meet the high-performance criteria.

Results after verification showed that the final performance after compaction was even slightly better than predicted by Amps.

A hard IP optimization design flow, used with compaction, can significantly help in reducing the timing closure bottleneck of deep-submicron-based designs.