SoC is redefining original ASIC model
By Suhel Dhanani, Product Marketing Manager, Development Tools, Altera Corp., San Jose, Calif., EE Times
May 15, 2000 (12:47 p.m. EST)
As ASIC vendors develop more system-on-chip devices, the real value they provide is shifting from a manufacturing-oriented added value to a design-based model.
Typically, the vendors come into the picture after the system designers have already written the HDL representation of the design and synthesized and simulated it. ASIC vendors do the place and route; target an in-house process technology; write the test program; and manufacture, assemble and package the finished integrated circuit. ASIC vendors generally play less of a role in system-level partitioning of the design, selection of the intellectual property (IP) cores, IP integration, and high-level coding and verification of the design, and they play more of a role in its physical implementation.
Two rapidly growing industry trends are conspiring to change the operating business model for ASIC companies: emergence of the pure foundry as a more cost-effective business model, a nd the rapid development of high-density, high-performance programmable logic that is cost-effective.
The pure foundry phenomenon is the biggest threat to the existing ASIC business model. ASIC vendors are always quick to point to their advanced state-of-the-art process technology as a competitive advantage. But foundries such as Taiwan Semiconductor Manufacturing Co. (Hsinchu, Taiwan) and UMC (Sunnyvale, Calif.) have shown that it makes a lot of sense to run a fab as a separate business.
That approach splits the risks associated with the ownership of a $2 billion to $3 billion factory, which is obsolete in three to four years, between innovative design houses and the foundry company. Fabs have to be full all the time because that is the only way they can pay for ultra-expensive process development, so when there is an oversupply of SRAMs the fab can crank out network processors and communication c hips. The pure-play foundries have shown that they can combine a state-of-the-art process technology with a compelling cost structure.
In the past, programmable logic devices (PLDs) have never been big enough, fast enough and low-cost enough to go into production. A significant number of designs these days face intense time-to-market pressures. Couple that fact with the low-volume requirements for industrial applications and the certainty that the design specifications will change, and it is easy to understand why hordes of design engineers are evaluating PLDs for production.
From their side, PLD vendors have made it easier by developing faster, bigger and less expensive chips with each new generation of PLDs. The problem for the ASIC vendors is that implementing a design in a PLD is almost trivial compared with implementing it in an ASIC.
Synthesis, placement and routing are almost pushbutton. No mask sets have to be developed, no test programs have to be written and wafers do not ha ve to be sorted. In addition, chips don't have to be tested with expensive equipment or baked and tested for reliability.
Generally speaking, PLDs are more expensive (per unit) than ASICs. In some cases they cannot accommodate a very-high-performance or very-high-density design. But in most cases where PLDs are achieving parity with respect to speed and density, ASICs have to concede that design to PLDs. Because of the rapidly mushrooming popularity of PLD devices, ASICs are relegated to designs with very high complexity, very high speed or high cost sensitivity. The key added values for such designs are bound to be in managing the silicon design complexity in terms of both density and performance requirements and in providing the lowest unit cost.
For an ASIC with true system-on-chip-level complexity, completing and verifying a design in an acceptable time is the key added value that an ASIC vendor has to provide. That involves an understanding of system-level design and access to intellect ual property offerings specific to the application.
ASIC vendors should strive to get involved in a design opportunity at the very front end. That typically dictates a high degree of system-level understanding.
System-level understanding also allows the ASIC vendor to partition the design among different ICs as well as determine the buy-vs.-make IP decision early in the design cycle.
Ideally, the ASIC vendor should have a library of IP functions in-house. Integrating IP in a large design is easiest if the ASIC vendor has the source code and access to the IP developers.
The last requirement is a team of expert silicon designers with in-depth experience of common EDA tools as well as internally developed tools for specific functions. The designers should be more than just place and route experts; ideally they should be designers with experience in HDL synthesis, verification and place and route, as well as considerable system understanding and the ability to work with architec ts from the system house as a team to implement the product definition in an IC.
The most advanced process technology does not always provide the lowest unit cost in the case of all ASICs. Ideally, ASIC companies should be able to choose the right manufacturing technology offered by different foundries. Today, however, they utilize whatever in-house technology they possess. Also, running a fab that is 85 percent full for two years and then 50 percent full for the next two years is hardly the most cost-effective manufacturing solution.
Designing a true SoC ASIC demands design skills that allow a product to be developed to meet the required competitive time-to-market window. The key problem in designing SoC chips lies with design productivity's not keeping pace with manufacturing advances.
The most important service that ASIC companies must provide to their system customers is design expertise, not access to manufacturing capacity. These changes would transform the ASIC value propositi on.
The companies that are in a position to provide such services today are those that have system-level design expertise in a particular vertical market segment, access to relevant IP cores, and silicon design expertise. Manufacturing can be contracted out to pure-foundry companies. Some of these skills exist at various IP provider companies, which normally specialize in providing IP cores for a particular vertical market segment (wireless, networking, etc.) and have the system-level understanding and access to an IP portfolio. Other skills are found at design services companies, which have skilled silicon design resources.
The concept of selling IP cores has yet to reach its full potential. Maybe that is because IP vendors have underestimated the amount of support that customers require in integrating the IP within their design. The customers might be really looking for a complete, verified SoC design within the time-to-market window and are not looking for in dividual IP cores. The combination of an IP provider and a design service company partnering with a foundry company can provide the services demanded of tomorrow's ASIC vendor.
Fabless chip companies like Broadcom Corp. (Irvine, Calif.) and Galileo Technology Ltd., which mainly sell application-specific standard products (ASSPs), could also quickly become forces in the ASIC business. That's because they have the relevant in-house-developed IP, design expertise and definite systems expertise in the chosen area.
The ASIC business needs to be redefined as a service business and not a product business. The IP and the expertise developed while providing ASIC services can be leveraged to develop an ASSP, which is a standard product business.
The combination of leading-edge process technology available via independent third-party foundry companies, the ever-increasing capabilities of programmable logic devices, and the increasing importance of IP and design expertise for SoC designs is con spiring to change the ASIC business model to a service-type business.