Chad Spackman, verification technologist, Open-Silicon
EETimes (2/2/2011 6:24 AM EST)
Electronic System Level (ESL) methodologies have been available for some time now. Who’s using them and what are they doing with them? Let’s begin with a broad and simplistic definition of ESL. ESL is ASIC or FPGA design and/or verification which leverages highly abstract software programming languages. By that definition, ESL enjoys noteworthy acceptance in the verification space. Object oriented programming languages such as C++, SystemC, SystemVerilog, and specman, are being used within larger verification frameworks allowing verification to be performed far above the pin and vector level that was once required. Verification using highly abstract testbenches is performed by engineers who understand the specification but not necessarily the design. Constrained randomized testing is used to obtain excellent functional coverage even in very large designs bound by simulation speed. The fundamental problem solved by ESL in the verification space is a nearly virtual high-level connection between a purely software test infrastructure and a pin level connection to the DUT.
What about with respect to design? Tools companies both large and small have been developing abstract design entry methods for more than a decade now. Acceptance is seemingly limited. What problems did ESL in design entry set out to solve and what has been accomplished?
To assess where ESL is today, let’s briefly have a look at the past progression of design entry methods and the fundamental motivations behind the progressions.
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