SoCs: Design tools -> Design flow is key to crafting a better SoC

One might imagine that a well-designed set of circuit blocks could be easily assembled into a working system-level chip. Indeed, the lure of the reusable intellectual property (IP) movement derives from the efficiency gains promised by assembling previously designed circuits. But is it really that easy? Experts looking at the problem in this week's focus on SoC design tools offer a sobering answer: You had better have a well-tested design-flow management strategy in place.

By now, the electronics industry has acquired a lot of experience in applying design tools to create viable circuits-up to a certain level of complexity. And in fairness to the industry's achievement, the level of complexity of current multimillion-transistor chips is high. But these high-complexity systems are now becoming simply circuit blocks in even more complex chips. In addition, different circuit types, which were never designed to work together on the same chip, are required to achieve a true system-level design. The possibilities for unpredictable interactions are high, especially when software is thrown into the mix.

Runtime Design Automation's Andrea Casotto thinks a missing piece in the SoC design puzzle is the management of data from many different IP blocks. The solution is an automated design flow system that continually updates the multiple files in a project.

As Andrea Casotto, president of Runtime Design Automation (Sunnyvale, Calif.) explains in his contribution, "with SoC, all of these once disparate components and methodologies interact with each other. The danger then is a lack of a complete representation of the operational relationships between the files-the flow." In that context, a simple change to a design may not result in the updating of all relevant files. Consequently, the capability of a sophisticated EDA tool would be irrelevant since it would be using the wrong data. Note that this problem has nothing to do with the specific circuit design tools being used.

Still, within the general problem area of design management, it is possible to pick out specific areas where special tools and design systems can be used effectively. One area being tackled by Sagantec Inc. (Fremont, Calif.) is the process of respinning "hard IP" for smaller-geometry processes. Hard IP is a circuit design represente d at the mask level, and Sagantec engineers are looking at tool groups that make it easy to rework the layout for different processes. The technique can be applied to simply reworking a design at the same scale for different fab lines, or it becomes a design-reuse strategy for SoCs.

CoWare Inc. (Santa Clara, Calif.) is dealing with the thorny problem of interfacing intellectual property that originates from different sources. Unless all the circuit blocks in a SoC design are produced by the same design team, a project merging IP will quickly bog down in the mostly manual task of reworking the interface circuitry. Co-Ware proposes to automate that process using the concept of a "virtual bus." A circuit is designed for the virtual bus specification and an automated tool then codes the interfaces.

Responding to the pressure of runaway design complexity, the EDA industry is forging new design tools that, once in the environment, can be used in new and unexpected ways. One consequence may be the r eshaping of different industry sectors such as the traditional ASIC business.