SoCs: DSP World, Cores -> Configurable DSP core eyes wireless

Over the next five years, the cellular markets will transition from second-generation (2G) standards such as GSM and IS-95 to third-generation (3G) standards such as UMTS and CDMA2000. These next-generation systems increase wireless data rates by an order of magnitude, enabling many new applications in cellular handsets. The 3G cellular phone will support much more than voice communication with added features such as Internet access, MP3 and video communication. These new features and functions, combined with the continuing trend for greater flexibility, smaller size and longer battery life, pose significant challenges to the main building block of state-of-the-art wireless handsets, the digital signal processor.

The DSP processing requirements of proposed 3G handsets are at least an order of magnitude greater than those for 2G. Complexity increases significantly as the requirement to support multiple data rates and modulation schemes must be met without compromising power dissipation or solution costs.

It has been assumed that wireless baseband chips for cellular phones will transition from programmable DSPs to low-cost ASIC designs, following the typical path of high-volume consumer applications. This assumption is not true for next-generation wireless handsets. These products are expected to support multiple radio protocols such as GSM, TDMA, CDMA and 3G while being at least software-radio capable. These dynamic requirements mandate use of programmable DSPs and prevent any near-term migration to fixed ASIC baseband solutions.

Similar jumps in performance requirements are expected in other advanced communications applications, such as broadband connectivity. These changes imply no immediate end to the appetite for inc reased DSP processing power. The traditional, brute-force approach to increase performance by adding more multiply-accumulate operations (MACs) or designing faster processors, is not capable of keeping up with growing application demands. DSP designers have responded by adding dedicated instructions to allow efficient implementation of intensive algorithms, such as the Viterbi decoder. These instructions are supported by dedicated hardware that provides accelerated convolutional coding for wireless apps.

Searching for more control, designers over the past two years have requested configurable DSP instruction sets and system-on-chip (SoC) architectures with scalable Mips. Initial architecture efforts toward configurable DSPs focused on modifying bus width, as with the Palm DSP core. However, designers quickly realized that most high-volume DSP applications can be implemented most efficiently using 16-bit DSPs, so there was little advantage in expanding the data bus width. Therefore, the challenge is t o obtain significantly more Mips than available in a traditional DSP architecture without simply increasing processor speed or adding MACs, since many of the required DSP Mips are not MAC-oriented. This revelation has spurred efforts to add accelerators and coprocessors to complement MAC-based DSP architectures.

One solution to such challenges is Infineon's Carmel DSP 20xx core, which combines the price/performance benefits of ASICsign with the flexibility of programmable DSP. The core's PowerPlug accelerators enable SoC designers to configure the instruction set and modify the core. Essentially, the PowerPlug interface lets designers add dedicated hardware that can perform unique single or multicycle tasks, in conjunction with the existing DSP core execution unit. By customizing the DSP data path through the PowerPlug extensions, wireless OEMs can bring differentiated products faster to market.

Basically, the Carmel DSP 20 core provides the scalability and performance required to support ad vanced communications applications without compromising power dissipation and hardware costs. PowerPlug technology decreases overall program code size and increases effective DSP Mips without raising the clock frequency, thus minimizing power dissipation.

The core's instruction set is a superset of the first-generation Carmel, featuring the configurable long instruction word (CLIW) architecture. CLIW instructions provide the foundation that enables application-specific, reconfigurable ISA and DSP core architecture, combining the benefits of very long instruction word (VLIW) with high performance and flexible control, and single instruction, multiple data (SIMD), offering compact code and low power.

Double the performance

With the new PowerPlug accelerators, the Carmel DSP 20 core more than doubles the performance of the first-generation Carmel DSP 10. PowerPlug accelerators can boost the DSP performance as much as needed for specific applications. For example, a designer of MAC -intensive applications can add two PowerPlug MACs to create a DSP architecture with quad-MAC performance per cycle. For graphic and video processing applications, four quad, 8-bit ALU PowerPlugs can easily support 16 pixel operations per cycle. Other video applications can benefit from MPEG-4 PowerPlug accelerators that are specifically designed for real-time MPEG applications.

Carmel DSP 20 PowerPlug-enabled development tools recognize PowerPlug-extended CLIW instructions. The PowerPlug accelerators are fully supported during debug and emulation, including the ability to view the internal registers of the PowerPlug accelerator.

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