Mark Williams, co-founder and CEO, Pulsic Ltd.
2/9/2011 10:43 AM EST
Each smaller sub-micron process technology brings a new set of physical problems for IC designers. Among the toughest of these problems are meeting electrical parasitic constraints and minimizing signal integrity issues in the interconnect routing while still reaching routing completion, controlling power consumption, staying within the specified die-size and speeding time to market. For digital designs, some of these concerns are addressed by automatic place and route tools. However, for custom IC designs, these issues remain largely unaddressed due to the inadequacy of the automation tools. In addition to custom design tools and flows, there is a need for standardization of data, including design constraints, an effort which is starting to gain momentum at the industry level.
This paper details the increasing problem of achieving parasitic-constraint closure during interconnect routing and how a shape-based routing methodology can help to solve these problems automatically while completing the routing of the design.
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