SoCs: IP Reuse -> Productized IP: more than pipe dream

However, IP can only deliver on the promise of better products faster if it can be used and reused easily.

The question is, how does one go about productizing an IP core?

A common misperception of most participants in the system-on-chip domain is the need for very detailed, thorough documentation. Claims that vast quantities of documentation are required are based on the precept that the efficiency tool being purchased is not intuitive to use. However, if an IP core comes packaged in an easy-to-use manner, and if it complies with constructs designers are familiar with, documentation takes on the sam e significance as it does with any EDA tool. It is important, but not as important as a robust feature set.

Furthermore, reading documentation is not a task designers are prone to do voluntarily. If an IP core can be productized to require less documentation, designers will prefer that core to others.

Targeting programmable logic dramatically reduces the number of potential integration flows, making it possible for IP providers to fully productize their cores for seamless integration into those flows. Users of high-density PLDs typically target a very limited number of tools, and verifying a core for those tools allows it to reach productization maturity for a market composed of tens of thousands of users.

Four-fifths done

By comparison, when designing IP for ASICs, providers typically must stop development at about 80 percent completion and wait for a customer to define the final details of the integration flow, which can include any number of third-party or custom-ow ned tools. In that model, the vendor is counting on the sales cycle to provide a buffer schedule to complete the core. With PLDs, an IP provider does not need to stop development and wait for final details from customers, because the target design flow for the vast majority of users is already known.

PLD IP cores that are fully productized to support the small number of integration flows utilized by customers make it possible to take productization one step further-providing an automatic installation into the design flow.

For example, imagine that when you receive an IP core, instead of a file with an indecipherable directory structure, you get an executable file, which launches an installation shield that copies all the appropriate files into the correct folders. Then, when you launch the core, a graphical user interface walks you through the different parameter options available, including a copy of the license agreement. The user interface then accesses all of the necessary files accordin g to your responses, and instantiates them in your design project.

This is not a pipe dream: IP companies have begun using exactly that kind of productization strategy with tools such as Altera's MegaWizard plug-in. The tool is available to IP providers at no charge to assist them in productizing their cores. The approach allows IP companies to implement the graphical user interface according to the parameterization levels defined by their core.

In the case of a design flow such as those commonly used for digital signal processing designs, providing a seamless flow from front-end tools to testbench outputs makes the usability of an IP core profoundly more significant. Sadly, most IP providers that target the ASIC space have not attempted to leverage known development flows to productize their cores.

Furthermore, with PLDs the cost for verification in target silicon is comparably low. Most IP consumers request a confirmation that the core runs in silicon. If the core runs in programmab le logic, ASIC users may have higher confidence, but the ASIC integration flow of that particular customer may introduce new risks that cannot be assessed by provider or customer. The only resolution is to execute in the target silicon process-an unrealistic expectation for an IP provider.

With PLDs, a core can be easily shown running in the customer's target silicon. Altera offers a family of prototyping and development boards based on its Apex and Flex device families. The boards are made available to IP providers to verify and demonstrate their cores to Altera customers.

Furthermore, providers use the term "parameterized" very loosely to mean that parameters can be set to different values. However, who has the power to set those parameters? In some cases, the act of setting parameters is a privilege protected by IP companies for themselves, allowing their customers little visibility and little leverage. The end result is that the core is more reusable for the provider and less reusable for the customer. Some cutting-edge IP companies have placed the control in the hands of the customers by delivering the parameter-setting power to the designer who will use-and much more likely reuse-that core.

There is no reason a potential customer should not be able to have a 30-day evaluation copy of an IP core. The technology to evaluate IP while protecting its source was enabled by the software industry years ago. Yet many IP providers hesitate to allow customers to investigate the functionality of the IP, creating a high degree of trepidation in the mind of the customer. What is the provider hiding? Is this core really available?

These barriers to sales can easily be removed by using encryption technology such as the OpenCore tool from Altera. This tool is an encryption program that allows IP providers to supply an encrypted Altera netlist to customers, who can then compile and simulate the design within the Quartus environment. The evaluation copy can be set to time-out after any time period the provider deems appropriate.

Why is IP pricing such a secret? Many IP companies maintain that pricing is highly sensitive information that must be protected from the public eye. Most often, the justification is the need to have a direct discussion with the customer before an appropriate price can be named. That approach is not scalable. A price associated with a standard product, without customization, is a data point that customers simply require. Not providing that information slows down the sales process.

If, for example, 100 customer inquiries per week are fielded, requiring a direct discussion with each customer will significantly hinder the efficient sale of the product.

Role of consulting

If IP is productized to require little documentation, to be seamlessly integrated into the target design flow and to enable evaluation in a known environment, consulting takes on an entirely new role. Now consulting services can be targeted specifically at system archi tecture optimization. The time-to-market benefit is realized. The IP provider's business is scaling up as he ships easy-to-use product to many customers who require much less support.

Consulting certainly has its place in the system-on-chip domain. However, with fully productized IP, consulting is no longer buried in a shroud of IP implementation issues because the IP is a complete product.

Consulting for systems-on-chip is exclusively concerned with the complex task of integrating many cores in a very short time frame. Whether this integration task is based on on-chip buses or platform-based design, it is still a challenging task, one that does not need to be complicated by cores that have not reached productization maturity.

By providing productized IP, suppliers will be able to scale their IP business by orders of magnitude while maintaining a reasonable cost of sales. Industry analysts have estimated that the levels of reuse in the next year will range from 50 to 90 percent. The o nly hope of achieving those levels is by productizing cores for broad appeal to a mass market-something that a glorified consulting business cannot achieve.

IP only works if the customer can modify and implement the designs. Placing the power of the IP product in the hands of the customer gives him or her control over the project's destiny. By using parameterization tools such as Altera's MegaWizard plug-in, real IP products that require no consulting component can be delivered to the market.