Decouple core for proper integration
Decouple core for proper integration
By Geert Rosseel, Senior Vice President, Product Development, Sonics Inc., Mountain View, Calif., EE Times
January 3, 2000 (3:17 p.m. EST)
System-on-chip (SoC) design presents huge challenges to the development team. Can a block be reused, or must it be redesigned? Can performance be met within the available market window? How will the design be verified and debugged? How can the design be made easy to debug?
On the surface, design reuse appears to address many of those issues. But many SoC design teams view the successful integration of intellectual-property (IP) cores as a significant challenge. The fundamental goal of "socketization," as the industry defines it, is to specify a set of guidelines for preparing a given functional block for reuse. We believe socketization in a vacuum does not work and that what is needed instead is an approach to fully address the issues faced when integrating multiple IP cores into an SoC design.
There are several flaws with current core-based reuse strategies. First, the proposed socket standards, such as the Virtual Socket Interfac e Alliance's Virtual Component Interface, address only simple data flows. As a result, the designer must deal with the remaining intercore communications requirements-control flows (such as interrupts, error signals and flow-control signals) and test signals (for debug and manufacturing test)-by hand-wiring them in an ad hoc fashion. Clearly, those socket standards were developed with the expectation that computer-style buses would continue to serve as the predominant on-chip interconnect fabric. But while computer buses are great for low-performance or computer-centric data flows, they leave hard real-time data flows, control and test signals as an "exercise for the reader."
Designers must rise to this challenge by building point-to-point links or other custom interconnect structures outside of the computer bus. However, since they cannot predict the final form and nature of those ad hoc inter-block communication schemes, system architects cannot accurately model them early in the design process. That unpredictability inevitably results in multiple design iterations, because the SoC rarely meets the product requirements as initially architected.
Another significant flaw in core-based reuse strategies is that they do not address the larger issues of core integration, such as frequency decoupling, system address map, interface timing and real-time throughput guarantees. As a result, the core design often becomes burdened with detailed system-level dependencies, particularly characteristics of other cores of the present system. This process tightly couples each core's functional behavior to that specific SoC implementation, severely hampering its reusability.
In other words, unless the core design and socketization process is informed by an effective chip integration strategy that decouples the core's functional behavior from interco re communications requirements, the socketization process may actually inhibit rather than enhance design reuse, predictability and complexity management. To put it simply, if you are "socketizing" your cores without regard to effective chip integration methods, don't even think about getting your chip to market on time.
To solve a number of problems created by the ad hoc approach, Sonics has developed an an alternative SoC integration strategy called communication system-based integration. The primary goals of the strategy are to create a unified, configurable, on-chip communication system that supports all data, control, test and debug flows; to deliver hardware-guaranteed bandwidth and latency to each core; to decouple intercore communications from core functionality; to provide a methodology for creating truly "componentized" cores with sufficient design independence to be reused without rework; and to simplify, speed and make more predictable the design, analysis, verification, debugging and te sting of multicore designs.
The power of this integration strategy to enable true core reusability hinges on two essential elements: an interface protocol that encompasses all communication flows into and from the core, and an integration methodology that effectively decouples system-level requirements from core functionality.
The first step in the strategy is to incorporate a comprehensive, standard interface protocol within the core that facilitates communication between cores. As with any socket standard, the protocol must be core-centric rather than system-interconnect-centric. In other words, if the core is to remain untouched as it moves from system to system, its interface must accommodate the unchanging requirements of the core rather than bend to the particular requirements of each system in which it is deployed.
The Open Core Protocol developed by Sonics is a flexible, extensible, processor- and bus-independent, point-to-point interface standard that allows functional bloc ks and cores to interoperate while maintaining functional independence from one another as well as from the underlying communications system. As such, the protocol is a linchpin to ensuring a fully decoupled on-chip communication system.
The next step in the communication system-based integration strategy is to implement a highly reconfigurable on-chip communication subsystem-a sort of customizable backplane in silicon-that implements the system-level requirements of the SoC. It must support traditional CPU-memory accesses, high-bandwidth links with real-time throughput requirements, as well as lower-speed peripherals. The backplane serves to unify all on-chip communications while providing configurable throughput guarantees to individual cores. As such, the backplane can replace dedicated connections between cores with logical connections over shared interconnect, while simultaneously supporting low-latency access from high-performance CPUs.
Each core connects to the backplane through an "ag ent"-the key to decoupling the cores. Agents implement a system-level communications protocol on top of the actual physical interconnect scheme. Each agent is highly customized to meet the system-level communications requirements of the core to which it is mated (for example, data width, address size and clock frequency).
The agent also provides for efficient utilization of system bandwidth and implements the system-address map, frequency decoupling, control-flow routing and real-time performance guarantees in terms of latency and bandwidth.
A significant side benefit of the communication system-based integration strategy is that it localizes all of the long, intercore wires within the backplane. That allows the designer to identify the long wires early in the design and to optimize them without affecting core interface timing.
The backplane must be configurable to ensure allocation of suf-ficient bandwidth for all communication flows inside the SoC. Sonics' particular version of the configurable subsystem-the SiliconBackplane-eliminates the need for expensive speed-matching FIFO resources at each core's interface by treating the SiliconBackplane's shared interconnect as a communication system.
Instead of relying on consecutive cycle bursts to increase transfer efficiency, the SiliconBackplane interleaves data transfers from different backplane agents on a per-cycle basis. Using the Sonics backplane compiler, a new backplane can be generated in a matter of hours.
Copyright © 2003 CMP Media, LLC | Privacy Statement