Planning reset strategy: Flow & functionality in OVC
Parag Goel, Pushkar Naik, Applied Micro Circuits Corp.
3/9/2011 8:01 AM EST
Overview
Reset strategy, which has long been a part and parcel of the design methodology, playing a vital role in the successful working of any given design, has become increasingly important on the verification methodology front. Reset forms a fundamental property of any protocol/system and is the first step in the sequence of operations done for any system bring up. The following write-up addresses this essential strategy to be followed during verification using an OVM-based test bench.
While developing an OVM–based IP (i.e. OVM Verification Component (OVC)), it is required to get a clear perspective on the way it behaves and recovers from reset application during the course of simulation.
![]() |
E-mail This Article | ![]() |
![]() |
Printer-Friendly Page |
|
Related Articles
- An Automated Flow for Reset Connectivity Checks in Complex SoCs having Multiple Power Domains
- SoC tool flow techniques for detecting reset domain crossing problems
- Four ways to build a CAD flow: In-house design to custom-EDA tool
- Capitalizing on the Architectural Flexibility of FPGAs with RISC-V and a Simplified Programming Flow
- Understanding Logic Equivalence Check (LEC) Flow and Its Challenges and Proposed Solution
New Articles
- When Traceability Catches What Verification Does Not
- Implementing C model integration using DPI in SystemVerilog
- Stop-For-Top IP model to replace One-Stop-Shop by 2025... and support the creation of successful Chiplet business
- Lossless Compression Efficiency of JPEG-LS, PNG, QOI and JPEG2000: A Comparative Study
- Four ways to build a CAD flow: In-house design to custom-EDA tool