Analog switches in D-PHY MIPI dual camera/dual display applications (Part 1 of 2)
Graham LS Connolly, Principal Engineer, and Tony Lee, Applications Engineer, Fairchild Semiconductor Corp.
EETimes (3/11/2011 3:05 PM EST)
The Mobile Industry Processor Interface Alliance (MIPI) is becoming more prevalent in the mobile device product industry. Mobile devices now commonly have dual display and/or dual camera architectures, particularly in the mid and higher functionality end products. The MIPI standard was originally defined as a point-to-point architecture, and consequently first generation processors, sensor modules and displays had a single MIPI port.
This article describes how, with the use of analog switches, the legacy processors can easily interface with dual cameras or dual displays without impacting the current system architecture and can, in actuality, enhance system performance by isolating the transmission line effects of the second camera (or display) loading the MIPI bus. In addition, the use of analog switches, due to their bidirectional capability, can also be used to multiplex co-processors to a single camera or display without impacting the performance.
As the new concept phones move to three displays, even the newer processors with 2x MIPI ports will benefit from an analog switch multiplexer device. Therefore, understanding the use of analog switches and their merits will enable the retrofit or upgraded feature set mobile devices to be designed with legacy or next generation processors.
E-mail This Article | Printer-Friendly Page |
Related Articles
- Analog switches in D-PHY MIPI dual camera/dual display applications (Part 2 of 2)
- Towards Self-Driving Cars: MIPI D-PHY Enabling Advanced Automotive Applications
- Dual Mode C-PHY/D-PHY: Enabling Next Generation of VR Displays
- A design of High Efficiency Combo-Type Architecture of MIPI D-PHY and C-PHY
- All you need to know about MIPI D-PHY RX
New Articles
- The Ideal Crypto Coprocessor with Root of Trust to Support Customer Complete Full Chip Evaluation: PUFcc gained SESIP and PSA Certified™ Level 3 RoT Component Certification
- Advanced Packaging and Chiplets Can Be for Everyone
- Timing Optimization Technique Using Useful Skew in 5nm Technology Node
- Streamlining SoC Design with IDS-Integrate™
- Last-Time Buy Notifications For Your ASICs? How To Make the Most of It
Most Popular
- Advanced Packaging and Chiplets Can Be for Everyone
- The Ideal Crypto Coprocessor with Root of Trust to Support Customer Complete Full Chip Evaluation: PUFcc gained SESIP and PSA Certified™ Level 3 RoT Component Certification
- Timing Optimization Technique Using Useful Skew in 5nm Technology Node
- Streamlining SoC Design with IDS-Integrate™
- System Verilog Assertions Simplified