English
Attofarad accuracy for high-performance memory design
Claudia Relyea, Mentor Graphics Corp.
EETimes (3/30/2011 9:52 AM EDT)
Relieving the pain of parasitic extraction
The future is here: phone, web browser, email, photo and video, all in one device at your finger tips, simultaneously. The evolution of IC design is in part driven by the demand for more memory with higher performance. Advanced process technologies enable more functionality, higher performance, and portability in chip design through smaller device sizes (Figure 1). These innovations pose interesting design challenges, which include new parasitic extraction issues that are affecting nanometer memory designs.
|
E-mail This Article | 
|
|
Printer-Friendly Page |
|
||||||
Related Articles
- Achieving High Performance Non-Volatile Memory Access Through "Execute-In-Place" Feature
- Choosing the right memory for high performance FPGA platforms
- Performance optimization using smart memory controllers, Part 1
- Optimizing High Performance CPUs, GPUs and DSPs? Use logic and memory IP - Part II
- Optimizing high-performance CPUs, GPUs and DSPs? Use logic and memory IP - Part I