Ashok Chandran, Sajeev Thomas & Saj Kapoor, Analog Devices Inc.
EETimes (5/23/2011 11:26 AM EDT)
Verification based on the Verification Methodology Manual (VMM) is a proven methodology for implementing block-level verification environments. Leveraging the block-level verification components at the system level provides significant improvement in verification quality and reduces the time required to meet coverage at system level. A system-level testbench brings a host of challenges that need to be addressed, including runtime, randomization quality, system memory management, multiple register access interfaces, clock domains and random stability. Block-to-system reuse methodology should be simple and scalable.
For a system-on-chip (SoC) with proprietary cores and system interfaces, coding an assembly language test that can exercise different modes of each peripheral component is not a scalable solution. Also, this does not fit well with the VMM-based flow, where there are several simulation threads accessing the peripheral together. For example, at the time that a peripheral is being configured, another thread may be reading from the same register space to check the interrupt status. This behavior cannot be modeled in an assembly test, where we have only a single instruction stream per core. The methodology replaces the core with a bus functional model (BFM) directly driving onto the system interface bus. Each block testbench is handled in different threads and can access the respective peripheral components. Usage of the VMM register abstraction layer (RAL) ensures that the block-level testbench undergoes minimal behavioral change when migrating to system level.
A system testbench needs to program the system components as per the peripheral requirement. For example, a universal asynchronous receiver/transmitter (UART) block will need the direct memory access (DMA) engine to be configured and memories initialized before transmitting. Since the system architecture is common for all peripherals, it makes more sense to provide a uniform platform and utility tasks that can configure the system as per the peripheral requirement. The multi-layer architecture ensures system support for each of the peripheral components. Each layer implements randomization and ensures maximum system and peripheral coverage.
The environment is optimized for performance by supporting thread management, conditional compilation and plug-and-play support for block-level testbenches. This means having a bottom-up approach where the block level needs to adhere to a basic, but broad, set of guidelines to ease integration.
This article describes the traditional method used in system-level verification and how the new approach improves it, explaining the layered architecture with an overview of the advantages it presents. Techniques to improve runtime with proper threading and memory management are described, as well as methods to overcome issues of large compilation time using separate compilation and multi-core compilation techniques. Finally, the article will touch on how this testbench avoids random stability issues using VMM record/playback method and supports test dumping in assembly formats.
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