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Specialization seen hindering SoC progress
By Nicolas Mokhoff, EE Times
March 6, 2002 (2:06 p.m. EST)
URL: http://www.eetimes.com/story/OEG20020306S0024
PARIS — The system-on-chip era is widening the gap between designers and manufacturers who have been forced by industry specialization into speaking different languages, a trend that does not bode well for future SoC projects, according to Taylor Scanlon, president and chief executive officer of Virtual Silicon Technology Inc. (Sunnyvale, Calif.), in a keynote at the Design Automation and Test in Europe conference.
The various parties involved in SoC design and use, from OEMs to design service bureaus, intellectual property providers, EDA vendors, and foundries, each have their own way of expressing the SoC design, Scanlon said. As a result, any misstep at any point in the design process can be misinterpreted, which can lead to delays, respins of designs and time-to-market hiccups.
Scanlon warned his Tuesday (March 5) audience of some 1,500 DATE attendees here that specialization will bite them if they don't find a way to "think outside the box."
"Thinking outside the box has become somewhat a cliche, but what I mean by it is that we, as corporations and as individuals, need to become aware of environments and responsibilities outside our own," said Scanlon. "If you are a designer, you have a chance to be a manager; a manager, an entrepreneur; an EDA manager can be thinking like an EDA developer."
Scanlon described a sort of 'student becomes the master' philosophy to the SoC design chain, indicating that the various design disciplines need to better understand each other. "The metrics used by ASIC designers are too different from that of the FPGA designers, but both need learning from each other," said Scanlon. "Otherwise the barriers that now exist will hinder design progress."
Scanlon said this view could have serious consequences in the era of 0.13-micron processes. "I have never seen so many problems in my years in the industry than the ones that are creeping up in bringing 0.13-micron chips into produc tion," he said. "I attribute that to the barriers put up by so many different interests in the design-to-manufacturing process."
If the industry as a whole and designers as individuals don't take it upon themselves to learn disciplines and technologies outside their specialties, then a change in the design process could ripple through the flow and "destroy everything that was worked on," Scanlon warned.
"If you know hardware, learn software. If you are a chip designer, learn system design. And in this global era, set your reference abroad — become a citizen of the world; learn the culture of fellow designers in Japan, Europe, China," said Scanlon. "Suppliers, as well, must balance competitive urges against the needs of the fragile design ecosystems that we have built."