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AES (ECB), 1 Billion Trace DPA Resistant Cryptographic Accelerator Cores
Basics of SoC I/O design: Part 2 - Hot swap & other implementation issues
Kannan Sadasivam and Sachin Gupta
EETimes (6/14/2011 11:04 PM EDT)
Having dealt in Part 1 with some of the basics of SoC I/O pin assignment, in this second part we will deal with a variety of implementation issues, including hot swap, threshold voltages, interrupts, pin assignments and Interfacing with the devices being operated at voltage other than SoC’s core voltage
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