The emergence and demand for 40G/100G systems is being driven by two main factors. The first is the increasing demand for higher data bandwidth driven by applications such as YouTube, Facebook and IP-TV and secondly by business and government demands for increasingly complex data intensive applications such as weather prediction, financial analysis, genomics research and design simulation. The recent emergence of cloud computing further adds to the communications challenge.
One of the key challenges with supporting 40G/100G links is that the SerDes must not only support emerging standards such as XLAUI (40G Ethernet) and CAUI (100G Ethernet) but must continue to support current and legacy interfaces such as 1Gbps Ethernet (SGMII) and 10Gbps Ethernet (XAUI). Multi-protocol support is essential to managing the transition to higher data rates while still supporting legacy standards.
High speed Ethernet has become the dominant standard for wireline communications, building on the ubiquity of 10Gbps Ethernet LAN. The new 40G/100G Ethernet standard leverages the existing serial 10Gbps Ethernet standard (10G BASE-R) to provide 4 to 10 times the bandwidth. The key element is a multi-lane approach that achieves aggregate data rates much higher than the fundamental electrical line rate. XLAUI (40G Ethernet) achieves 40Gbps using four 10.3125 Gbps lanes while CAUI (100G Ethernet) reaches 100Gbps with ten lanes of 10.3125 Gbps. The MAC frame architecture and link encoding (64b/66b) used by 10Gbps systems remains intact hence minimizing the impact of transitioning systems over from 10Gbps to 40Gbps and 100Gbps, respectively. Early adopters of 40G/100G Ethernet technology include the enterprise, data center, and core networking areas, most stressed by the explosive growth in demand.
MoSys's provides a multi-protocol SerDes solution which not only meets the requirements of emerging standards such as 40G/100G Ethernet but also current standards such as 10G Ethernet (XAUI, RXAUI) and 1G Ethernet (SGMII).
High Performance SerDes
A DLL-based half rate clock architecture forms the basis for the SerDes design, as shown in Figure 1. Since the PLL/DLL characteristics are the key determinant of high speed link performance, the PLL is designed to minimize jitter across the entire operating range while maximizing tuning range and loop bandwidth. The inherently low jitter LC oscillator based design uses programmable capacitances integrated into the voltage-controlled oscillator (VCO) to achieve the broad frequency range more typical of ring oscillator based PLLs. A precision bandgap reference provides a stable bias across temperature, process and voltage for the ultra-low jitter wideband LC PLL and associated DLL. The charge pump current, loop filter resistance and ripple capacitance are programmable to provide control over loop bandwidth and peaking, allowing SerDes performance to be fine-tuned for particular applications. In addition, the PLL design is optimized to minimize power consumption.
The transmitter (TX) serializes ten differential data lines onto a single high speed differential output using a 20-to-1 multiplexer. This output is fed to a 3-tap finite impulse response (FIR) filter based equalizer which predistorts the transmitted pulse to compensate for frequency-dependent channel loss characteristics. The final two stages, a predriver and a driver, boost the differential signal onto the channel and provide a nominal 100 ohm termination.
The receiver (RX) presents a nominal 100 ohm termination to the incoming differential data channel. The data stream passes through a variable gain amplifier (VGA) and continuous time linear equalizer (CTLE) with peaking control to compensate for transmission channel losses, followed by a non-linear adaptive decision feedback equalizer (DFE) to address intersymbol interference (ISI). The serial data is then sampled and sent to the deserializer logic before being output as ten differential signals. A phase interpolator takes inputs from the DLL, clock data recovery (CDR) logic, and bang bang phase detector, chose for its relative insensitivity to data patterns, to set the timing for the samplers.
Figure 1 SerDes Block Diagram
The SerDes delivers exceptional performance, including a wide PLL lock frequency range and excellent stability, low TX jitter, and high RX jitter tolerance, enabling BER of 10-12 to 10-15.
The open loop VCO output frequency range varies linearly from 4.5 GHz to 6 GHz with the calibration code, as shown in Figure 2. The measurements were made with a 173.43 MHz reference clock and demonstrate that the frequency is essentially independent of the four possible bandgap reference voltage (BGR) settings. The measured VCO frequency range of 4.5 GHz to 6GHz matches the design target and readily meets the requirements for both Ethernet 10G BASE-KR and CEI 11G with half rate clocking.
Transmitter or output jitter was characterized at 11.2 Gb/s for a PRBS 11 pattern. Jitter performance, as seen in Figure 3, is comparable to the best results published to date, with measured random jitter RJrms of 524 fs and total jitter TJ of 15.8 ps.
Figure 2 PLL VCO Open Loop Output Frequency
Figure 3 TX Output Jitter for a PRBS-11 Pattern at 11.2 Gbps
Figure 4 presents the transmitter eye diagram, showing a wide open eye with a width of 79.1 ps and a height of 349 mV. Tj is 0.17 UI with a margin of 25% on the CEI-11G specification.
Figure 4 Transmitter Eye Diagram
Receiver jitter tolerance performance is equally impressive, as shown in Figure 5 for 10.3 Gbps and in Figure 5 for 11.2 Gb/s.
Figure 5 Receiver Jitter Tolerance at 10.3 Gbps with a PRBS-31 Pattern
Figure 6 Receiver Jitter Tolerance at 11.2 Gbps with a PRBS-31 Pattern
Although the explosive growth of 40G/110G Ethernet and the broad adoption of the underlying 10G BASE-KR standard provided the impetus for the SerDes, the versatile design also more than meets the requirements for Optical Internetworking Forum (OIF) CEI 11G SR and SFP+, XFP and XFP+ modules.
MoSys's 10Gbps/11Gbps SerDes solution shows good performance characteristics for both 40G/100G Ethernet and CEI-11G solutions. The multi-protocol nature of the macro and the built in programmability allows flexibility in addressing a wide variety of applications and transmission environments.
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