Reusable IP, not system-level language, has become the new level of abstraction.
Ron Wilson, Editor-at-Large -- EDN, August 11, 2011
To deal with increasing complexity, you must increase your level of abstraction. So goes the truism. But as Moore’s Law accelerates the complexity of SOCs (systems on chips) toward escape velocity, where do you find a new abstraction to supplement RTL (register-transfer level)? Many observers, noting that textual, hardware-oriented RTL replaced schematics, argue by analogy that a system-description language, such as SystemC, will provide the next great abstraction. That scenario didn’t happen, however.
“Reusable IP [intellectual property] is the new level of abstraction,” says Ajoy Bose, chairman, president, and chief executive officer of Atrenta. If you examine what SOC-design teams are doing, you’ll find that creating an SOC is a process of finding, characterizing, and assembling previously used IP. Design-creation tools, whether SystemC, Verilog, or schematics, find a role only in filling in the blanks—the proprietary functions and connective tissue of the IC. But today’s design flows, as broad-spectrum-EDA companies, the foundries, and most SOC designers conceive them, have been slow to recognize this reality. Look at your tools, and you would think that every SOC begins with a set of functional requirements and a clean sheet of paper. Instead, consider what really goes on in an SOC design and what conclusions you can extract from these observations.
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