by Pete Hardee
The time and cost involved in designing multi-million gate SoCs (systems-on-chip) from scratch has become so great that few companies can afford totally new, original designs. Thus, some form of IP re-use is accepted as essential, but re-use has proven to be difficult to realize in practice. The industry's response has been to move to platform-based design as a way to speed new SoCs to market and control costs. Platform-based design is the pragmatic solution, both for semiconductor companies trying to deploy their IP portfolio effectively to help fill their fabs, and system houses trying to get new products to market quickly.
The platform-based design strategy is not just for hardware. As a matter of fact, it really pays off by leveraging existing software investments. The systems house can leverage existing application software tasks and middleware in several derivatives instead of reinventing the wheel each time. Software re-use is enabled by provision of a layer of firmware that hides inessential details of the platform hardware from the software, a layer known as the 'Hardware Abstraction Layer' (HAL). Plus, by creating a platform early in the design process, software designers can use that platform to develop their firmware well in advance of chip fabrication.
Unless IP re-use is considered from the start, traditional ASIC design makes it extremely difficult to change major IP blocks because all of the interfaces to the IP blocks are hard coded into the design. If major blocks are added, new hardware and software interfaces must be added to existing blocks.
Inter-twining an IP block's behavior with its interface in this manner means that, in order to offer a strong yet flexible IP portfolio, semiconductor vendors are forced to maintain a large IP repository including multiple variants of the same function for different busses. Add to this the fact that the models of many IP blocks are too low-level and it's clear to see why the much vaunted era of wide-scale IP re-use has not yet materialized.