SAN MATEO, Calif. Booted from the high end of the ASIC market by faster, more efficient cell-based chips, and from the low end by increasingly flexible and inexpensive FPGAs, the gate array is supposed to be dead. But several vendors, including the biggest name in gate arrays, haven't heard. They are fielding what they call a new class of ASIC platforms that could become strong candidates for the bulk of ASIC designs.
Market leader NEC Corp. will announce Monday (March 18) a custom-chip platform that reaches out to a growing class of disenfranchised systems companies that are unwilling to pony up for cell-based ASICs but find programmable logic too constraining. For its part, Chip Express Corp. last week said it has moved its Modular Array architecture to a 0.25-micron process and is working on an 0.18-micron generation.
AMI Semiconductor and Fujitsu Microelectronics are also fielding novel solutions that look to give cell-based ASICs and field-programmable gate arrays a run for the money.
NEC's Instant Silicon Solution Platform (ISSP) is mask-programmable like a gate array, but based on the same 0.13-micron process technology as the company's cell-based ASICs. Hence, the underlying logic and memory blocks are just as dense.
ASIC designers who try ISSP will have to give up some choices they had taken for granted, such as build-your-own embedded memory, and will sacrifice some logic density compared with standard cells. They will also have to assume responsibility for certain design steps that were the responsibility of the silicon vendor, such as floor planning.
But for customers in the oft-neglected "midvolume" range from a few thousand parts to just under 100,000 these inconveniences hardly matter, NEC said. ISSP's chief aim is to slash nonrecurring-engineering cost (NRE) tenfold and get silicon into customers' hands within weeks of netlist submission.
"They're much more complex than gate arrays but at th e same time enable a quicker turnaround time and lower NREs than a cell-based design," said Sudhir Mallya, senior manager of advanced product engineering for NEC's System LSI business unit (Santa Clara, Calif.). "They belong closer to a cell-based approach because the IP [intellectual property] is based on the same process technology."
NEC's decision to create a third path for ASIC designers comes on the heels of similar moves by Chip Express, which launched its revolutionary architecture at 0.35 micron several years ago, and AMI Semiconductor, whose XpressArray product family claims performance comparable to a standard-cell design.
The logic cell in the Chip Express architecture has a couple of logic gates, some multiplexers and inverters. The Santa Clara company has now abandoned its laser-programmed interconnect scheme in favor of the conventional gate array approach of configuring the wafer with the final two metal layers. This enables near-cell-based performance wit h only three masks for customization to the customer's netlist, the company said.
Similarly, AMI Semiconductor (Pocatello, Idaho) uses an array of low-level macros made up of NAND gates, converters, muxes and memory. AMIS has moved XpressArray to 0.18 micron.
Still other ASIC vendors are offering alternatives to standard cells and gate arrays. Fujitsu Microelectronics Inc. has launched "embedded arrays" with a fixed number of macros, memory and I/O. Because these general-purpose functions are predetermined, the wafers can be stocked and programmed later by customers. "Since the memory and I/O are fixed you can go back and do a metal mask option," said Yuk Yung, director of ASIC marketing for Fujitsu (San Jose, Calif.). "You can save about four weeks in the base wafer processing."
Until now, gate array architecture had gone through two distinct generations: channeled arrays and sea of gates. In both, the fundamental building block was not a logic gate but a pair of transistors fabricated on the w afer. Then the wafers were put into inventory without metal layers. The gate array vendor converted the customer netlist into a connection plan that used the metal layers to interconnect transistor pairs to form gates, flip-flops and so forth, and connect the gates and 'flops to implement the netlist.
Because only two or maybe three metal masks and a via mask were involved, the gate array could be fabricated from base wafers faster, at much lower NRE, than a cell-based design. Quick turnaround and low NRE became the gate array's drawing card, in exchange for which customers accepted reduced performance and density relative to cell-based designs.
Channeled and sea-of-gates arrays differed in one key aspect. In channeled arrays, strips of silicon were left vacant between rows of transistor pairs. This area was used for routing a critical issue with only two layers of metal available. As metal layers multiplied, vendors found they could fill the entire die with transistor pairs and simply route over some of them, considerably increasing density .
But as transistor speeds increased relative to interconnect speed, linking individual transistor pairs with metal became less competitive compared with designs in which handcrafted logic cells made up the basic logic elements. As a rule of thumb, when transistors are much faster than interconnect, larger logic elements make sense. That is why FPGAs, with their slow interconnect, tend to have relatively complex logic elements: typically one or two three-input lookup tables, a flip-flop and multiplexers.
Several years ago Chip Express realized this rule was just as true for gate arrays. It built its Modular Array architecture around the logic-cell array, an idea that had already proven itself in FPGAs. Chip Express inventories the base wafers at its foundry, United Microelectronics Corp., then provides tapeouts of the final masks so that UMC can take base wafers out of stock and finish the customization.
For AMIS, meanwhile, the driving issue was not just performance but the need to develop a gate array architecture to which FPGA designs could easily port. Again, the key ideas were a relatively complex logic cell, formed with transistors and lower metal layers, and customization using the top two metal layers and a via layer. AMI imports base wafers from foundry partner Taiwan Semiconductor Manufacturing Co. and fabricates the final metal layers at its Idaho facility .
NEC's arrays follow the same pattern. Although the company is keeping the details of its architecture under wraps, NEC says it is using a fairly complex logic cell with both combinatorial and sequential elements. "It's more complex than a sea of gates but at the same time it's fine-grained enough so that that it can be used with an ASIC design flow, so it doesn't need FPGA tools to design them," NEC's Mallya said.
NEC devices have five metal layers, three of them in the base array to create standard-logic and memory cells, and clock-routing, po wer, ground and debug circuitry. The final two layers implement the customer's netlist and provide added power routing needed for high-speed operation. The company offers three standard templates with 200,000 to more than a million usable logic gates and RAM bits. NEC said it can turn around a customer design in a week.
Because the underlying IP is based on the same 0.13-micron rules as its standard-cell process, there's little density penalty. "You always get a smaller function when you can prediffuse those IP blocks into the design," Mallya said. "We've given the option to use 16-kbit SRAM blocks, which is enough flexibility for the larger SRAMs and still keeps the higher integration levels for things like FIFOs that can be user programmable. If the user needed 16-kbit SRAM and used only 14 of them, they would still be better off going with the prediffused SRAM rather than making it programmable, because the area is so dense."
Overall logic density is about one-quarter that of cell-based designs, b ut still 10-times denser than a typical FPGA design, Mallya said.
This new generation of device from vendors like NEC, Chip Express, AMIS and Fujitsu offers much of the capability of midrange cell-based devices. The parts can implement embedded CPU cores, have significant on-chip memory and reach impressive operating frequencies.
With these capabilities, a purely ASIC design flow and time-to-samples of about a week, the parts can challenge not only large FPGAs which will lag behind the gate arrays in performance, power and cost but also cell-based ASICs, which will remain faster but carry higher NREs and turnaround time. Once again the middle of the ASIC market is up for grabs.